參數(shù)資料
型號： TMX320DM648ZUT900
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 120/166頁
文件大?。?/td> 1341K
代理商： TMX320DM648ZUT900
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6.15 Host-Port Interface (HPI) Peripheral
6.15.1 HPI Device-Specific Information
6.15.2 HPI Peripheral Register Description(s)
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
The DM647/DM648 devices include a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32).
The AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit
peripheral.
Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the
DM647/DM648.
An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the
EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA
channel 0.
Table 6-50. HPI Control Registers
HEX ADDRESS RANGE
0x0200 0000
ACRONYM
-
REGISTER NAME
COMMENTS
Reserved
PWREMU_MGMT has both
host/CPU read/write access.
0x0200 0004
PWREMU_MGMT
HPI power and emulation management register
0x0200 0008 - 0x0200 0024
0x0200 0028
0x0200 002C
-
-
-
Reserved
Reserved
Reserved
The host and the CPU have
read/write access to the
HPIC register.
(1)
0x0200 0030
HPIC
HPI control register
HPIA
HPI address register
(Write)
HPI address register
(Read)
Reserved
Reserved
The host has read/write
access to the HPIA registers.
The CPU has only read
access to the HPIA registers.
0x0200 0034
(HPIAW)
(2)
HPIA
(HPIAR)
(2)
-
-
0x0200 0038
0x0200 000C - 0x0200 007F
0x0200 0080 - 0x0200 FFFF
(1)
The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an
interrupt from the host.
There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes,
see the
TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide
(literature number
SPRUEL5
).
(2)
120
Peripheral Information and Electrical Specifications
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