參數(shù)資料
型號： TMX320C6414TGLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 46/140頁
文件大?。?/td> 2033K
代理商： TMX320C6414TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
IPU
DESCRIPTION
NAME
NO.
EMIFA (64-BIT) BUS ARBITRATION
||
AHOLDA
N22
O
IPU
EMIFA hold-request-acknowledge to the host
AHOLD
V23
I
IPU
EMIFA hold request from the host
ABUSREQ
P22
O
IPU
EMIFA bus request output
EMIFA (64-BIT) ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
||
AECLKIN
H25
I
IPD
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
is selected at reset via the pullup/pulldown resistors on the BEA[17:16] pins.
AECLKIN is the default for the EMIFA input clock.
AECLKOUT2
J23
O/Z
IPD
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT1
J26
O/Z
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
AARE/
ASDCAS/
ASADS/ASRE
J25
O/Z
IPU
EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable
synchronous interface-address strobe or read-enable
For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between ASADS and ASRE:
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.
AAOE/
ASDRAS/
ASOE
J24
O/Z
IPU
EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
AAWE/
ASDWE/
ASWE
K26
O/Z
IPU
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchro-
nous interface write-enable
ASDCKE
L25
O/Z
IPU
EMIFA SDRAM clock-enable (used for self-refresh mode). [EMIFA module only.]
If SDRAM is not in system, ASDCKE can be used as a general-purpose output.
ASOE3
R22
O/Z
IPU
EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
AARDY
L22
I
IPU
Asynchronous memory ready input
EMIFA (64-BIT) ADDRESS
||
AEA22
T22
AEA21
V24
AEA20
V25
AEA19
V26
AEA18
U23
AEA17
U24
O/Z
IPD
EMIFA external address (doubleword address)
AEA16
U25
AEA15
U26
AEA14
T25
AEA13
T26
AEA12
R23
AEA11
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
||These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
R24
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