參數(shù)資料
型號： TMX320C6414TGLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 104/140頁
文件大?。?/td> 2033K
代理商： TMX320C6414TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
104
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles for EMIFA and EMIFB modules
(see Figure 35)
NO.
600, 720
850, 1G
UNIT
MIN
MAX
3
th(HOLDAL-HOLDL)
Hold time, HOLD low after HOLDA low
E
ns
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
for EMIFA and EMIFB modules
§
(see Figure 35)
NO.
PARAMETER
600, 720
850, 1G
UNIT
MIN
MAX
1
td(HOLDL-EMHZ)
td(EMHZ-HOLDAL)
td(HOLDH-EMLZ)
td(EMLZ-HOLDAH)
td(HOLDL-EKOHZ)
td(HOLDH-EKOLZ)
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE
,
ASDCKE, ASOE3, and APDT.
For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and
BAWE/BSDWE/BSWE, BSOE3, and BPDT.
§The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
Delay time, HOLD low to EMIF Bus high impedance
2E
ns
2
Delay time, EMIF Bus high impedance to HOLDA low
0
2E
ns
4
Delay time, HOLD high to EMIF Bus low impedance
2E
7E
ns
5
Delay time, EMIF Bus low impedance to HOLDA high
0
2E
ns
6
Delay time, HOLD low to ECLKOUTx high impedance
2E
ns
7
Delay time, HOLD high to ECLKOUTx low impedance
2E
7E
ns
HOLD
HOLDA
EMIF Bus
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
C64x
C64x
1
3
2
5
4
ECLKOUTx
(EKxHZ = 0)
ECLKOUTx
(EKxHZ = 1)
6
7
For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.
For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and
BAWE/BSDWE/BSWE, BSOE3, and BPDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
Figure 35. HOLD/HOLDA Timing for EMIFA and EMIFB
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