參數(shù)資料
型號： TMX320C6414TGLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 124/140頁
文件大小： 2033K
代理商： TMX320C6414TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
124
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
(see Figure 55)
NO.
600
720
850
1G
UNIT
MASTER
SLAVE
MIN
MAX
MIN
MAX
4
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
12
2 12P
ns
5
Hold time, DR valid after CLKX high
4
5 + 24P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
Slave: CLKSTP = 10b, CLKXP = 1
(see Figure 55)
NO.
PARAMETER
600
720
850
1G
UNIT
MASTER§
MIN
SLAVE
MIN
MAX
MAX
1
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXL-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low#
T 2
T + 3
ns
2
H 2
H + 3
ns
3
Delay time, CLKX low to DX valid
2
4
12P + 2.8
20P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
H 2
H + 3
ns
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
4P + 3
12P + 17
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
8P + 2
16P + 17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S =
Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
#FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
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