- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382648 > TMX320C6413GTS500 (Texas Instruments, Inc.) Fixed-Point Digital Signal Processors PDF資料下載
參數(shù)資料
| 型號(hào)： | TMX320C6413GTS500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 87/140頁(yè) |
| 文件大?。?/td> | 1958K |
| 代理商： | TMX320C6413GTS500 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)當(dāng)前第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)
IEEE 1149.1 JTAG Compatibility Statement
87
April 2004
Revised May 2005
SPRS247E
4.10
IEEE 1149.1 JTAG Compatibility Statement
The TMS320C6413/C6410 DSP requires that both TRST and RESET be asserted upon power up to be
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both
resets are required for proper operation.
Note: TRST is synchronous and
must
be clocked by TCLK; otherwise, BSCAN may not respond as expected
after TRST is asserted.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a
JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be
released in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan
instructions work correctly independent of current state of RESET.
For maximum reliability, the TMS320C6413/C6410 DSP includes an internal pulldown (IPD) on the TRST pin
to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always
be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When
using this type of JTAG controller, assert TRST to intialize the DSP after powerup and externally drive TRST
high before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must occur to latch the state of EMU1 and
EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Normal/Emulation mode.
For more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN_WARNING section of the TMS320C6413/C6410 BSDL file contains information and
constraints regarding proper device operation while in Boundary Scan Mode.
For more detailed information on the C6413/C6410 JTAG emulation, see the
TMS320C6000 DSP Designing
for JTAG Emulation Reference Guide
(literature number SPRU641).
4.11
EMIF Device Speed
The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the
following requirements:
1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
up to 1 CE space of buffers connected to EMIF
EMIF trace lengths between 1 and 3 inches
143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.
Verification of AC timings is mandatory when using configurations other than those specified above. TI
recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the
Using IBIS Models
for Timing Analysis
application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
For more detailed information on the C6413/C6410 EMIF peripheral, see the
TMS320C6000 DSP External
Memory Interface (EMIF) Reference Guide
(literature number SPRU266).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMX320C6413GTSA400 | Aluminum Electrolytic Radial Leaded General Purpose Capacitor; Capacitance: 100uF; Voltage: 50V; Case Size: 8x11.5 mm; Packaging: Bulk |
| TMP320C6413GTSA400 | Fixed-Point Digital Signal Processors |
| TMX320C6413GTSA500 | Fixed-Point Digital Signal Processors |
| TMP320C6413GTSA500 | Fixed-Point Digital Signal Processors |
| TMX320C6413GTS | Fixed-Point Digital Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320C6413GTSA400 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMX320C6413GTSA500 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMX320C6413ZTS400 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMX320C6413ZTS500 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMX320C6413ZTSA400 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。