參數(shù)資料
型號： TMX320C6413GTS500
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 72/140頁
文件大?。?/td> 1958K
代理商： TMX320C6413GTS500
Clock PLL and Oscillator
72
April 2004
Revised May 2005
SPRS247E
PLLMULT
1
0
PLLCLK
CLKMODE0
CLKMODE1
CLKMODE2
CLKMODE3
C2
C1
EMI
Filter
3.3 V
/2
/8
/4
/6
00 01 10
CPU Clock
Peripheral Bus, EDMA
Clock
Timer Internal Clock
CLKOUT4, Peripheral Clock
CLKOUT6
/2
/4
EMIF
00 01 10
EK2RATE
(GBLCTL.[19,18])
ECLKOUT2
ECLKOUT1
PLL
x5, x6
x12, x16,
x18
x22, x24
10
μ
F
0.1
μ
F
AEA[20:19]
(For the PLL options, CLKMODE pins setup, and PLL clock frequency ranges,
see Table 4
1 and Table 4
2.)
Internal to C6413/10
PLLV
AECLKIN
CLKIN
OSCV
SS
OSCOUT
OSCV
DD
OSCIN
470 pF
470 pF
Osc.
CLKINSEL
1
0
C6
C5
C7
C8
R
S
R
B
Exact values for these components depend on choice of crystal. For recommended crystal and component values, see Table 4
3.
Do not connect any of these nodes to board power or ground if the oscillator is used. They are internally connected for proper operation.
If CLKIN is being used instead of the oscillator, then OSCV
DD
and OSCV
SS
may either be left open, or OSCV
DD
may be tied to CV
DD
and
OSCV
SS
may be tied to ground.
AUXCLK
for McASPs
OSC_DIS
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000
DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
DD
.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
E. If CLKIN is used instead of OSCIN, tie OSCIN to Ground to minimize noise and current. (Do not
leave OSCIN floating.)
Figure 4
1. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
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