參數(shù)資料
型號: TMX320C6413GTS500
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點(diǎn)數(shù)字信號處理器
文件頁數(shù): 115/140頁
文件大?。?/td> 1958K
代理商: TMX320C6413GTS500
Multichannel Audio Serial Port (McASP) Timing
115
April 2004
Revised May 2005
SPRS247E
7.9
Multichannel Audio Serial Port (McASP) Timing
Table 7
20. Timing Requirements for McASP (see Figure 7
24 and Figure 7
25)
NO.
400
500
UNIT
MIN
MAX
1
2
3
4
t
c(AHCKRX)
t
w(AHCKRX)
t
c(CKRX)
t
w(CKRX)
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
Pulse duration, ACLKR/X high or low
20
10
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACLKR/X ext
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
12.25
5
t
su(FRXC-KRX)
Setup time AFSR/X input valid before ACLKR/X latches data
Setup time, AFSR/X input valid before ACLKR/X latches data
5
5
5
5
5
5
5
5
6
t
h(CKRX-FRX)
Hold time AFSR/X input valid after ACLKR/X latches data
Hold time, AFSR/X input valid after ACLKR/X latches data
7
t
su(AXR-CKRX)
Setup time AXR input valid before ACLKR/X latches data
Setup time, AXR input valid before ACLKR/X latches data
8
t
h(CKRX-AXR)
Hold time AXR input valid after ACLKR/X latches data
Hold time, AXR input valid after ACLKR/X latches data
Table 7
21. Switching Characteristics Over Recommended Operating Conditions for McASP
(see Figure 7
24 and Figure 7
25)
NO.
PARAMETER
400
500
UNIT
MIN
MAX
9
10
11
12
t
c(AHCKRX)
t
w(AHCKRX)
t
c(CKRX)
t
w(CKRX)
Cycle time, AHCLKR/X
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
Pulse duration, ACLKR/X high or low
20
10
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACLKR/X int
ACLKR/X int
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
16.5
1
13
t
d(CKRX-FRX)
Delay time ACLKR/X transmit edge to AFSX/R output valid
Delay time, ACLKR/X transmit edge to AFSX/R output valid
5
2
12
5
12
10
10
14
t
d(CKRX-AXRV)
Delay time ACLKR/X transmit edge to AXR output valid
Delay time, ACLKR/X transmit edge to AXR output valid
1
2
0
0
15
t
dis(CKRX
AXRHZ)
Disable time, AXR high impedance following last data bit from
ACLKR/X transmit edge
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