參數(shù)資料
型號： TMX320C6413GTS500
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 13/140頁
文件大?。?/td> 1958K
代理商： TMX320C6413GTS500
Description
13
April 2004
Revised May 2005
SPRS247E
2.2
Description
The TMS320C64x
DSPs (including the TMS320C6413, TMS320C6410 devices) are the
highest-performance fixed-point DSP generation in the TMS320C6000
DSP platform. The TMS320C6413
and TMS320C6410 (C6413 and C6410) devices are based on the second-generation high-performance,
advanced VelociTI
very-long-instruction-word (VLIW) architecture (VelociTI.2
) developed by Texas
Instruments (TI). The high-performance, lower-cost C6413/C6410 DSPs enable customers to reduce system
costs for telecom, medical, industrial, office, and photo lab equipment. The C64x
is a code-compatible
member of the C6000
DSP platform.
With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C6413
device offers cost-effective solutions to high-performance DSP programming challenges.
With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the C6410
device offers cost-effective solutions to high-performance DSP programming challenges. The C6410 device
also provides excellent value for packet telephony and for other cost
sensitive applications demanding high
performance.
The C6413/C6410 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. The C64x
DSP core processor has 64 general-purpose registers of 32-bit
word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic
logic units (ALUs)— with VelociTI.2
extensions. The VelociTI.2
extensions in the eight functional units
include new instructions to accelerate the performance in video and imaging applications and extend the
parallelism of the VelociTI
architecture. The
C6413
can produce four 16-bit multiply-accumulates (MACs)
per cycle for a total of 2000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of
4000 MMACS. The
C6410
can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of
1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The
C6413/C6410 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000
DSP platform devices.
The C6413/C6410 uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit
memory space that is shared between program and data space [for
C6413
device] and the Level 2
memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space [for
C6410
device]. L2 memory can be configured as mapped memory, cache, or combinations of the two. The
peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus
modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a
user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output
port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory
interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and
peripherals.
Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be
individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin
from 2 to 32 time slots. The C6413/C6410 has sufficient bandwidth to support all six serial data pins
transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple
serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I
2
S)
format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430
encoded data channels simultaneously, with a single RAM containing the full implementation of user data and
channel status fields.
McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit
for each high-frequency master clock which verifies that the master clock is within a programmed frequency
range
.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMX320C6413GTSA400 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors
TMX320C6413GTSA500 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors
TMX320C6413ZTS400 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors
TMX320C6413ZTS500 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors
TMX320C6413ZTSA400 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors
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