參數(shù)資料
型號(hào): TMX320C6413GTS500
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù): 37/140頁
文件大?。?/td> 1958K
代理商: TMX320C6413GTS500
Interrupt Sources and Interrupt Selector
37
April 2004
Revised May 2005
SPRS247E
Table 2
21. TMS320C6413/C6410 EDMA Channel Synchronization Events
(Continued)
EDMA
CHANNEL
EVENT DESCRIPTION
EVENT NAME
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
AREVTE1
AREVTO1
AREVT1
ICREVT0
ICXEVT0
ICREVT1
ICXEVT1
GPINT8
GPINT9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
McASP1 receive even event
McASP1 receive odd event
McASP1 receive event
I2C0 receive event
I2C0 transmit event
I2C1 receive event
I2C1 transmit event
GP0 event 8
GP0 event 9
GP0 event 10
GP0 event 11
GP0 event 12
GP0 event 13
GP0 event 14
GP0 event 15
None
56
63
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the
TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide
(literature number SPRU234).
2.8
Interrupt Sources and Interrupt Selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 2
22. The highest-priority
interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00
INT_03) are non-maskable and fixed. The remaining interrupts (INT_04
INT_15) are maskable and
default to the interrupt source specified in Table 2
22. The interrupt source for interrupts 4
15 can be
programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector
Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
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