Synchronous DRAM Timing
105
April 2004
Revised May 2005
SPRS247E
AECLKOUTx
ACEx
ABE[3:0]
AEA[12:3]
AED[31:0]
AEA13
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
ASRE
AAWE/ASDWE/ASWE
AEA[22:14]
BE1
BE2
BE3
BE4
Bank
Column
D1
D2
D3
D4
8
7
6
5
5
5
1
3
2
8
4
4
4
1
READ
PDT
14
14
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
respectively. PDTRL equals 00 (zero latency) in Figure 7
12.
Figure 7
12. SDRAM Read Command (CAS Latency 3) for EMIFA