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參數(shù)資料
| 型號： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器） |
| 文件頁數(shù)： | 68/72頁 |
| 文件大小： | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
68
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
host-port-interface cycles
Figure 43 shows signals to the HPI. Figure 44 and Figure 45 show read and write cycles using the 16-bit
host-port interface. The HPI provides the host access to the internal data memory. To request access to the data
memory, the host asserts the HREQ control signal. When the data memory controller (DMC) is ready to grant
access to the host, it drives the HACK signal high. At that point, the host has control of the internal data memory
to read and write to the ’320C6201. When data transfer has completed, the host deasserts the HREQ signal.
When the ’320C6201 senses a change of state of the HREQ signal, it returns the HACK signal to the low state
and regains control of the internal data memory. The timing of the handshaking signals HREQ and HACK is
specified relative to the rising edge of CLKOUT1 and the rest of the host port timing parameters are specified
in CLKOUT1 clock cycles.
Host Port Interface
and
Device Configuration
(During Reset)
HA/DC [16:1]
HD[15:0]
HREQ
HACK
HR
HW
Figure 43. HPI and Device Configuration
timing requirements for the host-port cycles
NO
MIN
MAX
UNIT
1
tsu(HREQ-CKH)
tsu(HA-HRW)
th(HA-HRW)
tw(HRW)
tsu(HDHIZ-HR)
tsu(HD-HW)
th(HD-HW)
tp(HRW)
Setup time, HREQ valid before CLKOUT1 high
1
ns
4
Set-up time, HA valid before HR/HW low
2
cycles
5
Hold time, HA valid after HR/HW high
0
cycles
6
Pulse duration, width of HR and HW pulse
8
cycles
7
Set-up time, HD high impedance (not driven by C6X) before HR low
0
cycles
11
Set-up time, HD valid before HW low
2
cycles
12
Hold time, HD valid after HW high
0
cycles
13
Period between consecutive read and write cycles
12
cycles
switching characteristics for host-port cycles
NO
TEST CONDITIONS
MIN
MAX
UNIT
2
td(CKH-HACK)
tr(HACK)
td(HR-HDHIZ)
td(HRL-HD)
tv(HRH-HD)
Delay time, CLKOUT1 high to HACK valid
1
ns
3
Response time, HREQ high to HACK high
7
cycles
8
Delay time, HD high impedance after HR high
1
2
cycles
9
Delay time, HR low to HD valid
6
cycles
10
Valid time, HD after HR high
1
2
cycles
Values specified by design and not tested
P
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