參數(shù)資料
型號(hào): TMX320C6201
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors(1600MIPS at 200MHz,8個(gè)功能單元并行操作的DSP)
中文描述: 數(shù)字信號(hào)處理器(1600MIPS在200MHz,8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器)
文件頁數(shù): 32/72頁
文件大小: 1552K
代理商: TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock characteristics and timing (continued)
CLKIN
PLLV
PLLF
PLLG
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
P
CLKOUT1 Frequency Range 240–300 MHz –
CLKOUT1 Frequency Range 180–240 MHz –
CLKOUT1 Frequency Range 120–180 MHz –
CLKOUT1 Frequency Range 60–120 MHz –
CLKOUT1 Frequency Range 0–60 MHz –
P
P
R
CLKOUT2
CLKOUT1
1 1
0 1
1 0
0 0
– MULT
×
4
– MULT
×
2
– Reserved
– MULT
×
1
f(CLKOUT1)=f(CLKIN)
×
4
f(CLKOUT1)=f(CLKIN)
×
2
f(CLKOUT1)=f(CLKIN)
10
μ
F 0.1
μ
F
(bypass)
C1
C2
R1
NOTES: A. In CLKMODE x2 and x4, values for C1, C2, and R2 depend on CLKIN and CLKOUT1 frequencies.
B. For CLKMODE x1 the PLL circuit is bypassed and the choice of component values is irrelevant and the three
analog filter pins (PLLV, PLLF, PLLG) can remain unconnected.
EMI Filter
2.5 V
3.3 V
20 K
C
C
Figure 16. Clock PLL-Functional Diagram
P
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