參數(shù)資料
型號： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP)
中文描述： 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器）
文件頁數(shù)： 15/72頁
文件大?。?/td> 1552K
代理商： TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
CPU registers (continued)
Table 1. Control Registers
ABBREVIATION
NAME
DESCRIPTION
AMR
Addressing-mode register
Specifies whether to use linear or circular addressing for one of eight
registers. Also contains block sizes for circular addressing
CSR
Control status register
Contains the global-interrupt-enable bit, cache-control bits, and other
miscellaneous control and status bits
PCE1
Program counter
Contains the address of the fetch packet that contains the execute packet
in the E1 pipeline stage
IN
General-purpose input register
Contains 32 input signals
OUT
General-purpose output register
Contains 32 output signals
PDATA_O
Program data out
Contains 32 output signals. Used by the STP instruction to write to program
space
IER
Interrupt-enable register
Allows enabling/disabling of individual interrupts
IFR
Interrupt-flag register
Displays status of interrupts
ISR
Interrupt-set register
Allows to set pending interrupts manually
ICR
Interrupt-clear register
Allows to clear pending interrupts manually
ISTP
Interrupt-service table pointer
Points to the beginning of the Interrupt-service routine
IRP
Interrupt-return pointer
Contains the address used to return from a maskable interrupt
NRP
Non-maskable-interrupt return pointer
Contains the address used to return from non-maskable interrupt
Figure 3 shows the bit mapping for each of the ’C6201 control registers. Each control register bit map has a
corresponding entry in Table 1.
P
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