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參數(shù)資料
| 型號(hào)： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器） |
| 文件頁數(shù)： | 45/72頁 |
| 文件大?。?/td> | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
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NO.
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MIN
10
MAX
UNIT
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1
tc(CKO2)
Cycle time, period of CLKOUT2
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CLKOUT2
1
2
3
4
4
Figure 27. CLKOUT2 Timing
external memory interface
The external memory interface (EMIF) accesses data that is external to the chip. As shown in Figure 28, the
EMIF can receive requests for external data access from one of three functional blocks – the data memory
controller, the program/cache controller, or the DMA controller. The EMIF operation is configurable through
memory-mapped control registers accessed by the internal peripheral bus. See Table 5 and Figure 7. Every
EMIF program or data access uses the common 23-bit address bus and 32-bit data bus.
There are three spaces in the memory map, each of which is represented by one of three chip-enable
signals – CE2, CE1, and CE0. One of the chip-enables has to be asserted when the processors reads or writes
to any of the three memory-map external spaces 2, 1, or 0. Byte-enable control signals, BE3–BE0, select the
individual bytes, half-words, or words during EMIF-write cycles that originate from the data-memory controller.
All program and DMA cycles, as well as data-controller read cycles, are 32-bit – resulting in all four BE signals
being active. Data controller write cycles, however, can access byte or half-word data using individual BE
controls to select the active bytes. The addressing of bytes within each word is set by the LENDIAN pin to be
in the direction of high bits or low bits.
CE spaces 0 and 2 can be programmed to support different types of memory, but CE space 1 is restricted to
asynchronous memory cycles only, including ROM typically used to boot the system at power up. The ROM read
cycles are identical to CE0 and CE2 asynchronous SRAM cycles from the control-signal perspective, although
the CE1 cycles have the flexibility to pack ROM bytes into words if the ROM is 8- or 16-bits wide. The external
ROM size must be encoded by way of pins DC7–DC6 during reset.
The types of memory assigned to CE spaces 0 and 2 are also encoded by way of the DC pins during reset. Pins
DC3–DC2 specify the type of memory for the CE0 space and pins DC5–DC4 specify the type of memory for
space CE2. The supported memory types include asynchronous memory, synchronous burst SRAM
(SBSRAM), and synchronous DRAM (SDRAM). An additional external-control cycle can be used to drive CE
spaces 0 and 2 by setting appropriate bits in the EMIF global control register. External control cycles are different
from memory cycles in that they use request/ready handshaking to stretch individual bus cycles to
accommodate longer response times inherent in slower I/O devices. The EMIF provides a separate set of
control signals for each one of the memory cycles listed above (see Figure 28).
EMIF HOLD and HOLDA signals arbitrate the ownership of the EMIF bus between the host and the
TMX320C6201 DSP.
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