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參數(shù)資料
| 型號： | TMX320C6201 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(1600MIPS at 200MHz，8個功能單元并行操作的DSP) |
| 中文描述： | 數(shù)字信號處理器（1600MIPS在200MHz，8個功能單元并行操作的數(shù)字信號處理器） |
| 文件頁數(shù)： | 34/72頁 |
| 文件大小： | 1552K |
| 代理商： | TMX320C6201 |
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TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
power-down modes (idle1, 2, and 3)
Most of the operating power of CMOS logic is dissipated during circuit switching from one logic state to another.
By preventing some or all of chip logic from switching, significant power savings can be realized without losing
any data or operational context. Power-down modes idle1 and idle2 block the internal clock inputs at the
boundary of the selected blocks of logic, effectively preventing them from switching. Idle 1 shuts down the CPU
and Idle 2 shuts down both the CPU and the on-chip peripherals.The idle 2 mode is not available on the initial
release (TMX320C6201). Additional power savings are accomplished in power-down mode idle3, where the
entire on-chip clock tree (including multiple buffers) is “disconnected” at the clock source that is the clock PLL
(see Figure 17).
Clock
PLL
Power-
down
Logic
IFR
IER
CSR
PWRD
Peripherals
CPU
Idle 1
Idle 3
Idle 2
(see Note A)
’320C6201
CLKIN
CLKOUT2
CLKOUT1
RESET
NOTE A: Power-down mode idle2 is not implemented in the initial release of the
’320C6201.
Figure 17. Power-Down Mode Logic
31
16
15
14
13
12
11
10
9
0
Reserved
Enabled or
Non-Enabled
Interrupt
Wake
Enabled
Interrupt
Wake
Idle3
Idle2
Idle1
CSR
5
4
3
2
1
0
PWRD Field of CSR Register
Figure 18. CSR Register Power-Down Modes
P
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