參數(shù)資料
型號(hào)： TMX320C6201
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(1600MIPS at 200MHz，8個(gè)功能單元并行操作的DSP)
中文描述： 數(shù)字信號(hào)處理器（1600MIPS在200MHz，8個(gè)功能單元并行操作的數(shù)字信號(hào)處理器）
文件頁數(shù)： 63/72頁
文件大?。?/td> 1552K
代理商： TMX320C6201
TMX320C6201
DIGITAL SIGNAL PROCESSOR
SPRS051B – JANUARY 1997 – REVISED JUNE 1997
63
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
switching characteristics for the reset cycle
NO
TEST CONDITIONS
MIN
MAX
UNIT
3
tv(CLKOUT)
Valid time, CLKOUT1/2 after RESET low (depends
on PLLMODE) (see Note 4)
28
210
μ
s
5
td(CKH-CE)
Delay time, CLKOUT1 high to CE in high impedance
mode/driven
5
ns
6
td(CKH-BE)
Delay time, CLKOUT1 high to BE in high impedance
mode/driven
5
ns
7
td(CKH-A)
Delay time, CLKOUT1 high to EA in high impedance
mode/driven
0
5
ns
8
td(CKH-D)
Delay time, CLKOUT1 high to ED in high impedance
mode/driven
0
5.1
ns
9
td(CKH-XREQ)
Delay time, CLKOUT1 high to XREQ in high
impedance mode/driven
5
ns
10
td(CKH-OE)
Delay time, CLKOUT1 high to AXOE in high
impedance mode/driven
5
ns
11
td(CKH-WE)
Delay time, CLKOUT1 high to AXWE in high
impedance mode/driven
5
ns
12
td(CKH-ADS)
Delay time, CLKOUT1 high to SSADS in high
impedance mode/driven
5
ns
13
td(CKH-ADV)
Delay time, CLKOUT1 high to SSADV in high
impedance mode/driven
5
ns
14
td(CKH-SSOE)
Delay time, CLKOUT1 high to SSOE in high
impedance mode/driven
5
ns
15
td(CKH-SSWE)
Delay time, CLKOUT1 high to SSWE in high
impedance mode/driven
5
ns
16
td(CKH-SDA10)
Delay time, CLKOUT1 high to SDA10 in high
impedance mode/driven
5
ns
17
td(CKH-SDRAS)
Delay time, CLKOUT1 high to SDRAS in high
impedance mode/driven
5
ns
18
td(CKH-SDCAS)
Delay time, CLKOUT1 high to SDCAS in high
impedance mode/driven
5
ns
19
td(CKH-SDWE)
Delay time, CLKOUT1 high to SDWE in high
impedance mode/driven
5
ns
20
td(CKH-SDCKE)
Delay time, CLKOUT1 high to SDA10 low/driven
5
ns
21
td(CKH-SHD)
Delay time, CLKOUT1 high to HD in high impedance
mode/driven
0
5
ns
22
td(CKH-SHACK)
Delay time, CLKOUT1 high to HACK in low/driven
5
ns
23
td(RESET-TRI)
Delay time, RESET low to signals low (or driven
low-HACK)
2
cycles
24
td(RESET-DRV)
Delay time, RESET high to signals driven
2
cycles
Values derived from characterization data and not tested
Values specified by design and not tested
NOTE 4: The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, can need up to 210
μ
s to stabilize following
device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device
operation. See the PLL section for PLL lock times.
P
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