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參數(shù)資料
| 型號(hào)： | TMX20F2810PBKAEP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 38/159頁(yè) |
| 文件大?。?/td> | 2084K |
| 代理商： | TMX20F2810PBKAEP |
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Functional Overview
38
March 2004 Revised October 2004
SGUS051A
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of
the SPI. On the F281x and C281x, the port supports a 16-level, receive and transmit FIFO
for reducing servicing overhead.
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F281x and C281x, the port supports a 16-level, receive and
transmit FIFO for reducing servicing overhead.
SCI:
3.3
Register Map
The F281x and C281x devices contain three peripheral register spaces. The spaces are categorized as
follows:
Peripheral Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 34.
Peripheral Frame 1:
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 35.
Peripheral Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 36.
Table 34. Peripheral Frame 0 Registers
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
Device Emulation Registers
0x00 0880
0x00 09FF
384
EALLOW protected
reserved
0x00 0A00
0x00 0A7F
128
FLASH Registers§
0x00 0A80
0x00 0ADF
96
EALLOW protected
CSM Protected
Code Security Module Registers
0x00 0AE0
0x00 0AEF
16
EALLOW protected
reserved
0x00 0AF0
0x00 0B1F
48
XINTF Registers
0x00 0B20
0x00 0B3F
32
Not EALLOW protected
reserved
0x00 0B40
0x00 0BFF
192
CPU-TIMER0/1/2 Registers
0x00 0C00
0x00 0C3F
64
Not EALLOW protected
reserved
0x00 0C40
0x00 0CDF
160
PIE Registers
0x00 0CE0
0x00 0CFF
32
Not EALLOW protected
PIE Vector Table
0x00 0D00
0x00 0DFF
256
EALLOW protected
Reserved
0x00 0E00
0x00 0FFF
512
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction
disables writes. This prevents stray code or pointers from corrupting register contents.
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