參數(shù)資料
型號(hào)： TMX20F2810PBKAEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 120/159頁
文件大?。?/td> 2084K
代理商： TMX20F2810PBKAEP
Electrical Specifications
119
March 2004 Revised October 2004
SGUS051A
Table 624. SPI Slave Mode External Timing (Clock Phase = 1)
NO.
12
MIN
MAX
UNIT
ns
tc(SPC)S
tw(SPCH)S
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
tsu(SOMI-SPCH)S
tsu(SOMI-SPCL)S
Cycle time, SPICLK
8tc(LCO)
0.5tc(SPC)S10
0.5tc(SPC)S10
0.5tc(SPC)S10
0.5tc(SPC)S10
0.125tc(SPC)S
0.125tc(SPC)S
13§
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
ns
Pulse duration, SPICLK low (clock polarity = 1)
14§
Pulse duration, SPICLK low (clock polarity = 0)
ns
Pulse duration, SPICLK high (clock polarity = 1)
17§
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
ns
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
18§
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =0)
0.75tc(SPC)S
ns
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =1)
0.75tc(SPC)S
21§
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
0
ns
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
22§
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S
ns
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)S
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LS4
(SPIBRR
tc(LCO) = LSPCLK cycle time
§The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
or
LSPCLK
1)
Data Valid
22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
21
12
18
17
14
13
SPISTE
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 627. SPI Slave Mode External Timing (Clock Phase = 1)
相關(guān)PDF資料
PDF描述
TMS320LC2404APGA DSP CONTROLLERS
TMP320LC2401APAGA DSP CONTROLLERS
TMP320LC2401APAGS DSP CONTROLLERS
TMP320LC2401APGA DSP CONTROLLERS
TMP320LC2401APGEA DSP CONTROLLERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMX320C14FNL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor
TMX320C16PGL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor
TMX320C26FNL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor
TMX320C2811GHHA 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors
TMX320C2811GHHQ 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*