參數(shù)資料
型號(hào): TMX20F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 131/159頁
文件大?。?/td> 2084K
代理商: TMX20F2810PBKAEP
Electrical Specifications
130
March 2004 Revised October 2004
SGUS051A
Lead 1
Active
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XA[0:18]
XD[0:15]
XREADY(Synch)
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOHL-XZCSH)
td(XCOH-XA)
WS (Synch)
XZCS0AND1, XZCS2,
XZCS6AND7
XRD
XWE
XR/W
td(XCOH-XZCSL)
NOTES:
A.
All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an
access to meet this requirement.
During alignment cycles, all signals will transition to their inactive state.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
For each sample, setup time from the beginning of the access can be calculated as
D = (XWRLEAD + XWRACTIVE + n 1) tc(XTIM) tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
B.
C.
D.
E.
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
th(XD)XWEH
tsu(XRDHsynchH)XCOHL
tsu(XRDYsynchL)XCOHL
DOUT
td(XWEL-XD)
tdis(XD)XRNW
th(XRDYsynchL)
th(XRDYsynchH)XZCSH
= Don’t care. Signal can be high or low during this time.
Legend:
See Note E
See Note D
See
Notes
and B
See Note C
te(XRDYsynchH)
Figure 633. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A
N/A
N/A
1
0
1
3
1
0 = XREADY
(Synch)
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