參數(shù)資料
型號: TMX20F2810PBKAEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號處理器
文件頁數(shù): 140/159頁
文件大小: 2084K
代理商: TMX20F2810PBKAEP
Electrical Specifications
138
March 2004 Revised October 2004
SGUS051A
ac
Rs
ADCIN0
Cp
10 pF
Ron
1 k
1.25 pF
Ch
Switch
Typical Values of the Input Circuit Components:
Switch Resistance (Ron):
Sampling Capacitor (Ch):
Parasitic Capacitance (Cp): 10 pF
Source Resistance (Rs):
1 k
1.25 pF
50
28x DSP
Source
Signal
Figure 637. ADC Analog Input Impedance Model
6.30.4
ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
PWDNADC
Request for
ADC
Conversion
td(BGR)
td(PWD)
Figure 638. ADC Power-Up Control Bit Timing
Table 641. ADC Power-Up Delays
MIN
TYP
MAX
UNIT
td(BGR)
Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register
(PWDNBG and PWDNREF) are to be set to 1 before the PWDNADC bit is enabled.
7
8
10
ms
td(PWD)
Delay time for power-down control to be stable. Bit 7 of the ADCTRL3 register
(PWDNADC) is to be set to 1 before any ADC conversions are initiated.
These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions
are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at the same time.
20
50
μ
s
ms
1
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