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www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
F05 Flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the Flash Read and Flash Program and Erase sections.
Flash Protection Keys
The
A384
device
provides
flash
protection
keys.
These
four
32-bit
protection
keys
prevent
program/erase/compaction operations from occurring until after the four protection keys have been matched by
the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the A384 are
located in the last 4 words of the first 8K sector. For more detailed information on the flash protection keys and
the FMPKEY control register, see the "Optional Quadruple Protection Keys" and "Programming the Protection
Keys" portions of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
Flash Read
The A384 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to
0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
NOTE:
The flash external pump voltage (VCCP) is required for all operations (program, erase,
and read).
Flash Pipeline Mode
When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz (versus a system
clock frequency of 24 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read with no wait states
when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).
NOTE:
After a system reset, pipeline mode is disabled (FMREGOPT[0] = 0). In other words,
the A384 device powers up and comes out of reset in non-pipeline mode.
Furthermore, setting the flash configuration mode bit (GBLCTRL[4]) overrides pipeline
mode.
Copyright 2005–2008, Texas Instruments Incorporated
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