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www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
Table 2. Terminal Functions (continued)
TERMINAL
INTERNAL
INPUT
OUTPUT
PULLUP/
DESCRIPTION
VOLTAGE(1)(2)
CURRENT(3)
NAME
PZ
PGE
PULLDOWN
SYSTEM MODULE (SYS)
Bidirectional clock out. CLKOUT can be
CLKOUT
57
81
3.3 V
4 mA
programmed as a GIO pin or the output of
SYSCLK, ICLK, or MCLK.
Input master chip power-up reset. External VCC
PORRST
85
118
3.3 V
IPD (20 A)
monitor circuitry must assert a power-on reset.
Bidirectional reset. The internal circuitry can
assert a reset, and an external system reset can
assert a device reset.
On this pin, the output buffer is implemented as
RST
86
121
3.3 V
4 mA
IPU (20 A)
an open drain (drives low only).
To ensure an external reset is not arbitrarily
generated, TI recommends that an external
pullup resistor be connected to this pin.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
Analog watchdog reset. The AWD pin provides
a system reset if the WD KEY is not written in
time by the system, providing an external RC
network circuit is connected. If the user is not
using AWD, TI recommends that this pin be
AWD
25
36
3.3 V
4 mA
connected to ground or pulled down to ground
by an external resistor.
For more details on the external RC network
circuit, see the TMS470R1x System Module
Reference Guide (literature number SPNU189).
TEST/DEBUG (T/D)
Test clock. TCK controls the test hardware
TCK
54
76
2 mA
IPD (20 A)
(JTAG).
Test data in. TDI inputs serial data to the test
TDI
52
74
2 mA
IPU (20 A)
instruction register, test data register, and
programmable test address (JTAG).
Test data out. TDO outputs serial data from the
test instruction register, test data register,
TDO
53
75
4 mA
IPD (20 A)
identification register, and programmable test
address (JTAG).
Test enable. Reserved for internal use only. TI
recommends that this pin be connected to
TEST
87
124
3.3 V
IPD (20 A)
ground or pulled down to ground by an external
resistor.
Serial input for controlling the state of the CPU
TMS
11
17
2 mA
IPU (20 A)
test access port (TAP) controller (JTAG).
Serial input for controlling the second TAP. TI
TMS2
10
16
2 mA
IPU (20 A)
recommends that this pin be connected to VCCIO
or pulled up to VCCIO by an external resistor.
Test hardware reset to TAP1 and TAP2.
IEEE Std 1149.1 (JTAG) Boundary-Scan Logic.
TRST
100
144
IPD (20 A)
TI recommends that this pin be pulled down to
ground by an external resistor.
Copyright 2005–2008, Texas Instruments Incorporated
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