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參數(shù)資料
型號: TMS470R1A384PZQ
廠商: Texas Instruments
文件頁數(shù): 31/62頁
文件大?。?/td> 0K
描述: IC RISC MCU 384K FLASH 100-LQFP
標準包裝: 90
系列: TMS470
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 48MHz
連通性: CAN,C2Slb,I²C,SCI,SPI
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 384KB(384K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 2.05 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-LQFP
包裝: 管件
配用: 296-23003-ND - KIT DEV KICKSTART TMS470
Switching Characteristics Over Recommended Operating Conditions for External Clocks
(1) (2) (3)
CLKOUT
tw(COH)
tw(COL)
ECLK
tw(EOH)
tw(EOL)
www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
SYSCLK or MCLK(4)
0.5tc(SYS) - tf
ns
tw(COL)
Pulse duration, CLKOUT low
ICLK: X is even or 1(5)
0.5tc(ICLK) - tf
ICLK: X is odd and not 1(5)
0.5tc(ICLK) + 0.5tc(SYS) - tf
SYSCLK or MCLK(4)
0.5tc(SYS) - tr
ns
tw(COH)
Pulse duration, CLKOUT high
ICLK: X is even or 1(5)
0.5tc(ICLK) - tr
ICLK: X is odd and not 1(5)
0.5tc(ICLK) - 0.5tc(SYS) - tr
N is even and X is even or odd
0.5tc(ECLK) - tf
ns
tw(EOL)
Pulse duration, ECLK low
N is odd and X is even
0.5tc(ECLK) - tf
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) - tf
N is even and X is even or odd
0.5tc(ECLK) - tr
ns
tw(EOH)
Pulse duration, ECLK high
N is odd and X is even
0.5tc(ECLK) - tr
N is odd and X is odd and not 1
0.5tc(ECLK) - 0.5tc(SYS) - tr
(1)
X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
(2)
N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3)
CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
(4)
Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
(5)
Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).
Figure 7. CLKOUT Timing Diagram
Figure 8. ECLK Timing Diagram
Copyright 2005–2008, Texas Instruments Incorporated
37
Product Folder Link(s): TMS470R1A384
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