SPNS110E – AUGUST 2005 – REVISED MAY 2008 .............." />
參數(shù)資料
型號: TMS470R1A384PZQ
廠商: Texas Instruments
文件頁數(shù): 50/62頁
文件大小: 0K
描述: IC RISC MCU 384K FLASH 100-LQFP
標準包裝: 90
系列: TMS470
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 48MHz
連通性: CAN,C2Slb,I²C,SCI,SPI
外圍設備: DMA,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 384KB(384K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 2.05 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-LQFP
包裝: 管件
配用: 296-23003-ND - KIT DEV KICKSTART TMS470
MULTI-BUFFERED A-TO-D CONVERTER (MibADC)
SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on VSS
and VCC, from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO
unless otherwise noted.
Resolution
10 bits (1024 values)
Monotonic
Assured
Output conversion code
00h to 3FFh [00 for VAI ≤ ADREFLO; 3FFh for VAI ≥ ADREFHI]
Table 12. MibADC Recommended Operating Conditions(1)
MIN
MAX
UNIT
ADREFHI
A-to-D high-voltage reference source
VSSAD
VCCAD
V
ADREFLO
A-to-D low-voltage reference source
VSSAD
VCCAD
V
VAI
Analog input voltage
VSSAD– 0.3
VCCAD + 0.3
V
Analog input clamp current(2)
IAIC
–2
2
mA
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
(1)
For VCCAD and VSSAD recommended operating conditions, see the "Device Recommended Operating Conditions" table.
(2)
Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Table 13. Operating Characteristics Over Full Ranges of Recommended Operating Conditions(1)(2)
PARAMETER
DESCRIPTION/CONDITIONS
MIN
TYP
MAX UNIT
Ri
Analog input resistance
250
500
Conversion
10
pF
Ci
Analog input capacitance
Sampling
30
pF
IAIL
Analog input leakage current
-1
1
A
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
5
mA
Conversion range over which specified
CR
ADREFHI - ADREFLO
3
3.6
V
accuracy is maintained
Difference between the actual step width
EDNL
Differential nonlinearity error
±2
LSB
and the ideal value. See Figure 24.
Maximum deviation from the best straight
line through the MibADC. MibADC
EINL
Integral nonlinearity error
±2
LSB
transfer characteristics, excluding the
quantization error. See Figure 25.
Maximum value of the difference
E TOT
Total error/absolute accuracy
between an analog value and the ideal
±2
LSB
midstep value. See Figure 26.
(1)
VCCAD = ADREFHI
(2)
1 LSB = (ADREFHI - ADREFLO)/2
10 for the MibADC
54
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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