tw(SDAH) tr(SCL) t
參數(shù)資料
型號(hào)： TMS470R1A384PZQ
廠商： Texas Instruments
文件頁(yè)數(shù)： 43/62頁(yè)
文件大小： 0K
描述： IC RISC MCU 384K FLASH 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： TMS470
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 48MHz
連通性： CAN，C2Slb，I²C，SCI，SPI
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 53
程序存儲(chǔ)器容量： 384KB（384K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 1.71 V ~ 2.05 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 100-LQFP
包裝： 管件
配用： 296-23003-ND - KIT DEV KICKSTART TMS470
I2C TIMING
tw(SDAH)
tr(SCL)
th(SDASCLL)
th(SCLLSDAL)
tw(SCLH)
tf(SCL)
th(SCLLSDAL)
tsu(SCLHSDAL)
tw(SP)
tsu(SCLHSDAH)
SDA
SCL
Stop
Start
Repeated
Stop
tc(SCL)
tw(SCLL)
tsu(SDASCLH)
SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
Table 11 below assumes testing over recommended operating conditions.
Table 11. I2C Signals (SDA and SCL) Switching Characteristics(1)
STANDARD
FAST MODE
MODE
PARAMETER
UNIT
MIN
MAX
MIN
MAX
tc(I2CCLK)
Cycle time, I2C module clock
75
150
75
150
ns
tc(SCL)
Cycle time, SCL
10
2.5
s
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START condition)
4.7
0.6
s
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated START condition)
4
0.6
s
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
s
tw(SCLH)
Pulse duration, SCL high
4
0.6
s
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
ns
th(SDA-SCLL)
Hold time, SDA valid after SCL low
For I2C bus devices
0 3.45(2)
0
0.9
s
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
4.7
1.3
s
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
4.0
0.6
s
tw(SP)
Pulse duration, spike (must be suppressed)
0
50
ns
Cb
(3)
Capacitive load for each bus line
400
pF
(1)
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2)
The maximum th(SDA-SCLL) for I2C bus devices needs to be met only if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3)
Cb = The total capacitance of one bus line in pF.
A.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
B.
The maximum th(SDA-SCLL) needs only be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL
signal.
C.
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250
ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL
signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr max + tsu(SDA-SCLH).
D.
Cb = total capacitance of one bus line in pF. If mixed with HS=mode devices, faster fall-times are allowed.
Figure 19. I2C Timings
48
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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