參數(shù)資料
型號(hào)： TMS44100P
廠商： Texas Instruments, Inc.
英文描述： 4194304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES
中文描述： 4194304字1位動(dòng)態(tài)隨機(jī)存取記憶體
文件頁(yè)數(shù)： 9/25頁(yè)
文件大?。?/td> 383K
代理商： TMS44100P
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4x100-60
’4x100P-60
’4x100-70
’4x100P-70
’4x100-80
’4x100P-80
UNIT
MIN
110
130
40
60
60
60
100
15
10
40
140
10
MAX
MIN
130
153
45
68
70
70
100
18
10
50
130
10
MAX
MIN
150
175
50
75
80
80
100
20
10
60
150
10
MAX
tRC
tRWC
tPC
tPRWC
tRASP
tRAS
tRASS
tCAS
tCP
tRP
tRPS
tWP
tASC
tASR
tDS
tRCS
tCWL
tRWL
tWCS
tWSR
tWTS
tCAH
tDHR
tDH
tAR
tRAH
tRCH
tRRH
tWCH
tWCR
tWHR
tWTH
Cycle time, random read or write (see Note 8)
Cycle time, read-write (see Note 8)
Cycle time, page-mode read or write (see Notes 8 and 9)
Cycle time, page-mode read-write (see Note 8)
Pulse duration, RAS low, page mode (see Note 10)
Pulse duration, RAS low, nonpage mode (see Note 10)
Pulse duration, RAS low, self refresh
Pulse duration, CAS low, (see Note 11)
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
Precharge time after self refresh using RAS
Pulse duration, write
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data (see Note 12)
Setup time, W high before CAS low
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low before CAS low (early-write operation only)
Setup time, W high (CBR refresh only)
Setup time, W low (test mode only)
Hold time, column address after CAS low
Hold time, data after RAS low (see Note 13)
Hold time, data (see Note 12)
Hold time, column address after RAS low (see Note 13)
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 14)
Hold time, W high after RAS high (see Note 14)
Hold time, W low after CAS low (early-write operation only)
Hold time, W low after RAS low (see Note 13)
Hold time, W high (CBR refresh only)
Hold time, W low (test mode only)
Delay time, column address to W low
(read-write operation only)
ns
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 000
10 000
100 000
10 000
100 000
10 000
10 000
10 000
10 000
0
0
0
0
0
0
0
0
0
0
0
0
15
15
0
10
10
10
50
10
50
10
0
0
10
50
10
10
18
18
0
10
10
15
55
15
55
10
0
0
15
55
10
10
20
20
0
10
10
15
60
15
60
10
0
0
15
60
10
10
tAWD
30
35
40
ns
tCHR
tCRP
tCSH
NOTES:
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
Delay time, RAS low to CAS high
10
0
60
10
0
70
10
0
80
ns
ns
ns
8. All cycle times assume tT = 5 ns.
9. To assure tPC min, tASC should be
≥
5 ns.
10. In a read-write cycle, tRWD and tRWL must be observed.
11. In a read-write cycle, tCWD and tCWL must be observed.
12. Referenced to the later of CAS or W in write operations
13. The minimum value is measured when tRCD is set to tRCD min as a reference.
14. Either tRRH or tRCH must be satisfied for a read cycle.
A
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