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參數(shù)資料
| 型號： | TMS44100P |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4194304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4194304字1位動態(tài)隨機存取記憶體 |
| 文件頁數(shù)： | 3/25頁 |
| 文件大?。?/td> | 383K |
| 代理商： | TMS44100P |
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS
page cycle time used.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS4x100 to operate at a higher data bandwidth than
conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than
when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after t
CAC
max (access time from CAS low),
if t
AA
max (access time from column address) has been satisfied. If column addresses for the next cycle are
valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of t
CAC
or t
CPA
(access time from rising edge of CAS).
address (A0–A10)
Twenty-two address bits are required to decode 1 of 4194304 storage cell locations. Eleven row-address bits
are set up on inputs A0 through A10 and latched onto the chip by the row-address strobe (RAS). The eleven
column-address bits are set up on A0 through A10 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating
the output buffer, as well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on W selects the read mode
and a logic low selects the write mode. W can be driven from standard TTL circuits (TMS44100/P) or
low-voltage TTL circuits (TMS46100/P) without a pullup resistor. The data input is disabled when the read mode
is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the
entire cycle, permitting common I/O operation.
data in (D)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS is already low and the data is strobed in by W with setup and hold times referenced to this signal.
data out (Q)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS is brought
low. In a read cycle, the output becomes valid after the access time interval t
CAC
(which begins with the negative
transition of CAS) as long as t
RAC
and t
AA
are satisfied. The output becomes valid after the access time has
elapsed and remains valid while CAS is low; CAS going high returns it to the high-impedance state. In a
delayed-write or read-write cycle, the output follows the sequence for the read cycle.
A
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