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參數(shù)資料
| 型號： | TMS44100P |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4194304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4194304字1位動態(tài)隨機(jī)存取記憶體 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 383K |
| 代理商： | TMS44100P |
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x100P) to retain data. This
can be achieved by strobing each of the 1024 rows (A0–A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the
output. This is accomplished by holding CAS at V
IL
after a read operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden-refresh
cycle.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter t
CSR
) and holding it low after RAS
falls (see parameter t
CHR
). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 300-
μ
A (TMS46100P) or 500-
μ
A
(TMS44100P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125
μ
s while holding RAS low for less than 1
μ
s. To minimize current consumption, all
input levels need to be at CMOS levels (V
IL
≤
0.2 V, V
IH
≥
V
CC
– 0.2 V).
self refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100
μ
s. The chip is then refreshed by an on-board oscillator. No external address is required
because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy t
CHS
. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200
μ
s followed by a minimum of eight initialization cycles
is required after full V
CC
level is achieved. These eight initialization cycles must include at least one refresh
(RAS-only or CBR) cycle.
test mode
An industry-standard design-for-test (DFT) mode is incorporated in the TMS4x100 and TMS4x100P. A CBR
cycle with W low (WCBR) cycle is used to enter the test mode. In the test mode, data is written into and read
from eight sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data-out
terminal goes high. If any one bit is different, the data-out terminal goes low. Any combination of read, write,
read-write, or page-mode cycles can be used in the test mode. The test-mode function reduces test times by
enabling the 4-Mbit DRAM to be tested as if it were a 512K DRAM, where row address 10, column address 10,
and column address 0 are not used. A RAS-only or CBR refresh cycle is used to exit the DFT mode.
A
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