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| 型號(hào)： | TMS44100P |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4194304-WORD BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4194304字1位動(dòng)態(tài)隨機(jī)存取記憶體 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 383K |
| 代理商： | TMS44100P |
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4x100-60
’4x100P-60
’4x100-70
’4x100P-70
’4x100-80
’4x100P-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tCSR
tCHS
tCWD
tRAD
tRAL
tCAL
tRCD
tRPC
tRSH
tRWD
tTAA
tTCPA
tTRAC
Delay time, CAS low to RAS low (CBR refresh only)
5
5
5
ns
Hold time, CAS low after RAS high, self refresh
–50
–50
–50
ns
Delay time, CAS low to W low (read-write operation only)
15
18
20
ns
Delay time, RAS low to column address (see Note 15)
15
30
15
35
15
40
ns
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to CAS high
30
35
40
ns
Delay time, RAS low to CAS low (see Note 15)
20
45
20
52
20
60
ns
Delay time, RAS high to CAS low
0
0
0
ns
Delay time, CAS low to RAS high
15
18
20
ns
Delay time, RAS low to W low (read-write operation only)
60
70
80
ns
Access time from address (test mode)
35
40
45
ns
Access time from column precharge (test mode)
40
45
50
ns
Access time from RAS (test mode)
65
75
85
ns
tREF
Refresh time interval
’4x100
16
16
16
ms
’4x100P
128
128
128
ms
tT
Transition time
2
50
2
50
2
50
ns
NOTE 15: The maximum value is specified only to assure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC = 5 V
CL = 100 pF
Output Under Test
Output Under Test
CL = 100 pF
(b) ALTERNATE LOAD CIRCUIT
(a) LOAD CIRCUIT
RL = 218
R1 = 828
R2 = 295
Figure 1. Load Circuits for Timing Parameters
A
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