參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 34/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
2.4.15 System Configuration Interface
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 2-20. PWM Terminal Functions (continued)
TERMINAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NAME
COUT3-
B6 /
GIO077 /
PWM2C /
RTO2
COUT2-
B5 /
GIO076 /
PWM2D /
RTO3
COUT1-
B4 /
GIO075 /
PWM3A
COUT0-
B3 /
GIO074 /
PWM3B
FIELD /
GIO070 /
R2 /
PWM3C
EXTCLK /
GIO069 /
B2 /
PWM3D
NO.
Digital Video Out: VENC settings determine function GIO: GIO[077]
PWM2C
RTO2
E3
I/O/Z
V
DD_VOUT
Digital Video Out: VENC settings determine function GIO: GIO[076]
PWM2D
RTO3
E4
I/O/Z
V
DD_VOUT
Digital Video Out: VENC settings determine function GIO: GIO[075]
PWM3A
F3
I/O/Z
V
DD_VOUT
Digital Video Out: VENC settings determine function GIO: GIO[074]
PWM3B
F4
I/O/Z
V
DD_VOUT
Video Encoder: Field identifier for interlaced display formats GIO: GIO[070]
Digital Video Out: R2
PWM3C
H4
I/O/Z
V
DD_VOUT
Video Encoder: External clock input, used if clock rates > 27 MHz are needed,
e.g. 74.25 MHz for HDTV digital output GIO: GIO[069] Digital Video Out: B2
PWM3D
PD
G3
I/O/Z
V
DD_VOUT
The DM355 provides interfaces for system configuration and boot load.
Table 2-21. System/Boot Terminal Functions
TERMINAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NAME
NO.
Async EMIF: Address bus bit 13
GIO: GIO[067]
System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Used
to drive boot status LED signal (active low) in ROM boot modes.
Async EMIF: Address bus bit 12
GIO: GIO[066]
System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
Async EMIF: Address bus bit 11
GIO: GIO[065]
System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration.
AECFG[3] sets default fo PinMux2.EM_D15_8. AEMIF default bus width (16 or 8
bits).
Async EMIF: Address bus bit 10
GIO: GIO[064]
System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration.
AECFG[2:1] sets default fo PinMux2.EM_BA0. AEMIF EM_BA0 definition:
(EM,_BA0, EM_A14, GIO[054], rsvd)
Async EMIF: Address bus bit 09
GIO: GIO[063]
System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration.
AECFG[2:1] sets default fo PinMux2.EM_BA0. AEMIF EM_BA0 definition:
(EM,_BA0, EM_A14, GIO[054], rsvd)
EM_A13/
GIO067/
BTSEL[1]
PD
V
DD
V19
I/O/Z
EM_A12/
GIO066/
BTSEL[0]
PD
V
DD
U19
I/O/Z
EM_A11/
GIO065/
AECFG[3]
PU
V
DD
R16
I/O/Z
EM_A10/
GIO064/
AECFG[2]
PU
V
DD
R18
I/O/Z
EM_A09/
GIO063/
AECFG[1]
PD
V
DD
P17
I/O/Z
(1)
(2)
(3)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
Specifies the operating I/O supply voltage for each signal. See
Section 5.3
,
Power Supplies
for more detail.
PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 k
resistor should be used.)
Device Overview
34
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