參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 32/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
2.4.12 Clock Interface
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 2-17. SPI Terminal Functions (continued)
TERMINAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NAME
NO.
Standard CCD Analog Front End (AFE): Not used
YCC 16-bit: time multiplexed between chroma. CB/CR[07]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is
time multiplexed between luma and chroma of the upper channel.
Y/CB/CR[07]
SPI: SPI2 clock
GIO: GIO[101]
Standard CCD Analog Front End (AFE): Raw[13]
YCC 16-bit: time multiplexed between chroma. CB/CR[05]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is
time multiplexed between luma and chroma of the upper channel.
Y/CB/CR[07]
SPI: SPI2 chip select
GIO: GIO[099]
Standard CCD Analog Front End (AFE): Raw[12]
YCC 16-bit: time multiplexed between chroma. CB/CR[04]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is
time multiplexed between luma and chroma of the upper channel.
Y/CB/CR[04]
SPI: SPI2 Data in
GIO: GIO[0998]
Standard CCD Analog Front End (AFE): Not used
YCC 16-bit: time multiplexed between chroma. CB/CR[06]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is
time multiplexed between luma and chroma of the upper channel.
Y/CB/CR[06]
SPI: SPI2 Data out
GIO: GIO[100]
CIN7/
GIO101/
SPI2_SCLK
PD
N3
I/O/Z
V
DD_VIN
CIN5/
GIO099/
SPI2_SDENA[0]
PD
M3
I/O/Z
V
DD_VIN
CIN4/
GIO098/
SPI2_SDI/
SPI2_SDENA[1]
PD
L4
I/O/Z
V
DD_VIN
CIN6/
GIO100/
SPI2_SDO/
PD
K5
I/O/Z
V
DD_VIN
The DM355 provides interface with the system clocks.
Table 2-18. Clocks Terminal Functions
TERMINAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NAME
CLKOUT1
/ GIO018
CLKOUT2
/ GIO017
CLKOUT3
/ GIO016
MXI1
NO.
CLKOUT: Output Clock 1
GIO: GIO[018]
CLKOUT: Output Clock 2
GIO: GIO[017]
CLKOUT: Output Clock 3
GIO: GIO[016]
Crystal input for system oscillator (24 MHz or 36 MHz)
Output for system oscillator (24 MHz or 36 MHz). When the MX02 is not used,
the MX02 signal can be left open.
Crystal input for video oscillator (27 MHz) Optional, use only if 27MHz derived
from MXI1 and PLL does not provide sufficient performance for Video DAC.
When the MXI2 is not used and powered down, the MXI2 signal should be left
as a No Connect
Output for video oscillator (27 MHz) Optional, use only if 27MHz derived from
MXI1 and PLL does not provide sufficient performance for Video DAC When the
MXO2 is not used and powered down, the MXO2 signal should be left as a No
Connect.
D12
I/O/Z
V
DD
A11
I/O/Z
V
DD
C11
I/O/Z
V
DD
A9
I
V
DD
MXO1
B9
O
V
DD
MXI2
R1
I
V
DD
MXO2
T1
O
V
DD
(1)
(2)
(3)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
Specifies the operating I/O supply voltage for each signal. See
Section 5.3
,
Power Supplies
for more detail.
PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 k
resistor should be used.)
Device Overview
32
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