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| 型號(hào)： | TMS320DM355_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media System-on-Chip (DMSoC) |
| 中文描述： | 數(shù)字媒體系統(tǒng)芯片（DMSoC） |
| 文件頁(yè)數(shù)： | 115/158頁(yè) |
| 文件大?。?/td> | 1319K |
| 代理商： | TMS320DM355_07 |
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5.9 Video Processing Sub-System (VPSS) Overview
5.9.1
Video Processing Front-End (VPFE)
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
The DM355 contains a Video Processing Sub-System (VPSS) that provides an input interface (Video
Processing Front End or VPFE) for external imaging peripherals such as image sensors, video decoders,
etc.; and an output interface (Video Processing Back End or VPBE) for display devices, such as analog
SDTV displays, digital LCD panels, HDTV video encoders, etc.
In addition to these peripherals, there is a set of common buffer memory and DMA control to ensure
efficient use of the DDR2 burst bandwidth. The shared buffer logic/memory is a unique block that is
tailored for seamlessly integrating the VPSS into an image/video processing system. It acts as the primary
source or sink to all the VPFE and VPBE modules that are either requesting or transferring data from/to
DDR2. In order to efficiently utilize the external DDR2 bandwidth, the shared buffer logic/memory
interfaces with the DMA system via a high bandwidth bus (64-bit wide). The shared buffer logic/memory
also interfaces with all the VPFE and VPBE modules via a 128-bit wide bus. The shared buffer
logic/memory (divided into the read & write buffers and arbitration logic) is capable of performing the
following functions. It is imperative that the VPSS utilize DDR2 bandwidth efficiently due to both its large
bandwidth requirements and the real-time requirements of the VPSS modules. Because it is possible to
configure the VPSS modules in such a way that DDR2 bandwidth is exceeded, a set of user accessible
registers is provided to monitor overflows or failures in data transfers.
The VPFE or Video Processing Front-End block is comprised of the CCD Controller (CCDC), Image Pipe
(IPIPE), and Hardware 3A Statistic Generator (H3A). These modules are described in the sections that
follow.
5.9.1.1
CCD Controller (CCDC)
The CCDC is responsible for accepting raw (unprocessed) image/video data from a sensor (CMOS or
CCD). In addition, the CCDC can accept YUV video data in numerous formats, typically from so-called
video decoder devices. In the case of raw inputs, the CCDC output requires additional image processing
to transform the raw input image to the final processed image. This processing can be done either
on-the-fly in the Preview Engine hardware ISP or in software on the ARM and MPEG/JPEG co-processor
subsystems. In parallel, raw data input to the CCDC can also used for computing various statistics (3A,
Histogram) to eventually control the image/video tuning parameters. The CCDC is programmed via control
and parameter registers. DM355 performance is enhanced by its dedicated hard-wired MPEG/JPEG
co-processor (MJCP). The MJCP performs all the computational operations required for JPE and MPEG4
compression. These operations can be invoked using the xDM (xDIAS for Digital Media) APIs. For more
information, refer to the
xDIAS-DM (xDIAS for Digital Media) User's Guide
(
SPRUEC8
). The following
features are supported by the CCDC module.
Support for conventional Bayer pattern.
Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to the
external timing generator.
Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware
support for higher number of fields, typically 3-, 4-, and 5-field sensors).
Support for up to 75 MHz sensor clock (270-MHz speed grade device)
Support for REC656/CCIR-656 standard (YCbCr 422 format, either 8- or 16-bit).
Support for YCbCr 422 format, either 8- or 16-bit with discrete H and VSYNC signals.
Support for up to 14-bit input.
Support for color space conversion
Generates optical black clamping signals.
Support for shutter signal control.
Support for digital clamping and black level compensation.
Fault pixel correction based on a lookup table that contains row and column position of the pixel to be
corrected.
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DM355 Peripheral Information and Electrical Specifications
115
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS320DM6446_07 | Digital Media System-on-Chip |
| TMS320F2801X | Digital Signal Processors |
| TMS320F2809_07 | Digital Signal Processors |
| TMS320F28335_1 | Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP |
| TMS4024 | 9 X 64 DIGITAL STORAGE BUFFER (FIFO) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320DM355-216 | 制造商:Texas Instruments 功能描述:DMSOC ARM926EJ-S CORE 216MHZ 337BGA 制造商:Texas Instruments 功能描述:DMSOC, ARM926EJ-S CORE, 216MHZ, 337BGA |
| TMS320DM355CZCE135 | 制造商:Texas Instruments 功能描述: |
| TMS320DM355CZCE216 | 功能描述:處理器 - 專(zhuān)門(mén)應(yīng)用 Dig Media System-on- Chip RoHS:否 制造商:Freescale Semiconductor 類(lèi)型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| TMS320DM355CZCE270 | 功能描述:IC DGTL MEDIA SOC 337NFBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TMS320DM3x, DaVinci™ 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| TMS320DM355CZCEA13 | 功能描述:處理器 - 專(zhuān)門(mén)應(yīng)用 Dig Media System-on- Chip RoHS:否 制造商:Freescale Semiconductor 類(lèi)型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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