參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 15/158頁
文件大小： 1319K
代理商： TMS320DM355_07
www.ti.com
P
2.4.2
Image Data Output - Video Processing Back End (VPBE)
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 2-5. CCD Controller/Video Input Terminal Functions (continued)
TERMINAL
NAME
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
NO.
Standard CCD Analog Front End (AFE): Raw[05]
YCC 16-bit: Time multiplexed between chroma: Y[05]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]
GIO: GIO[091]
Standard CCD Analog Front End (AFE): Raw[04]
YCC 16-bit: Time multiplexed between chroma: Y[04]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]
GIO: GIO[090]
Standard CCD Analog Front End (AFE): Raw[03]
YCC 16-bit: Time multiplexed between chroma: Y[03]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]
GIO: GIO[089]
Standard CCD Analog Front End (AFE): Raw[02]
YCC 16-bit: Time multiplexed between chroma: Y[02]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]
GIO: GIO[088]
Standard CCD Analog Front End (AFE): Raw[01]
YCC 16-bit: Time multiplexed between chroma: Y[01]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]
GIO: GIO[087]
Standard CCD Analog Front End (AFE): Raw[00]
YCC 16-bit: Time multiplexed between chroma: Y[00]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]
GIO: GIO[086]
Horizontal synchronization signal that can be either an input (slave mode) or an
output (master mode). Tells the CCDC when a new line starts.
GIO: GIO[085]
Vertical synchronization signal that can be either an input (slave mode) or an output
(master mode). Tells the CCDC when a new frame starts.
GIO: GIO[084]
Write enable input signal is used by external device (AFE/TG) to gate the DDR
output of the CCDC module. Alternately, the field identification input signal is used
by external device (AFE/TG) to indicate which of two frames is input to the CCDC
module for sensors with interlaced output. CCDC handles 1- or 2-field sensors in
hardware.
GIO: GIO[083]
Pixel clock input (strobe for lines C17 through Y10)
GIO: GIO[0082]
YIN5/
GIO091
PD
M5
I/O/Z
V
DD_VIN
YIN4/
GIO090
PD
P3
I/O/Z
V
DD_VIN
YIN3/
GIO089
PD
R3
I/O/Z
V
DD_VIN
YIN2/
GIO088
PD
P4
I/O/Z
V
DD_VIN
YIN1/
GIO087
PD
P2
I/O/Z
V
DD_VIN
YIN0/
GIO086
PD
P5
I/O/Z
V
DD_VIN
CAM_HD/
GIO085
PD
N5
I/O/Z
V
DD_VIN
CAM_VD
GIO084
PD
R4
I/O/Z
V
DD_VIN
CAM_WEN
_FIELD\
GIO083
PD
R5
I/O/Z
V
DD_VIN
PCLK/
GIO082
PD
T3
I/O/Z
V
DD_VIN
The Video Encoder/Digital LCD interface module in the video processing back end has an external signal
interface for digital image data output as described in
Table 2-7
and
Table 2-8
.
The digital image data output signals support multiple functions / interfaces, depending on the display
mode selected. The following table describes these modes. Parallel RGB mode with more than RGB565
signals requires enabling pin multiplexing to support (i.e., for RGB666 mode).
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