參數(shù)資料
型號(hào): TMP86CH09NG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP32
封裝: 0.400 INCH, 1.78 MM PITCH, LEAD FREE, PLASTIC, SDIP-32
文件頁數(shù): 78/120頁
文件大?。?/td> 1743K
代理商: TMP86CH09NG
Page 49
TMP86FH09ANG
5. I/O Ports
The TMP86FH09ANG have 4 parallel input/output ports as follows.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
input data should be externally held until the input data is read from outside or reading should be performed several
timer before processing. Figure 5-1 shows input/output timing examples.
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This
timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro-
gram.
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
port.
Note: The positions of the read and write cycles may vary, depending on the instruction.
Figure 5-1 Input/Output Timing (Example)
Primary Function
Secondary Functions
Port P0
8-bit I/O port
External interrupt input, Timer/Counter input/output, serial interface input/output,
serial PROM mode control input/output.
Port P1
7-bit I/O port
External interrupt input and divider output
Port P2
3-bit I/O port
External interrupt input and STOP mode release signal input
Port P3
8-bit I/O port
Analog input, STOP mode release signal input and Timer/Counter input/output
Instruction
execution cycle
Input strobe
Data input
:LD A,(x)
Fetch cycle
Read cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Instruction
execution cycle
Output strobe
Data Output
: LD (x), A
Fetch cycle
Write cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
(a) Input timing
(b) Output timing
Old
New
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