參數(shù)資料
型號： TMP86CH09NG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, 1.78 MM PITCH, LEAD FREE, PLASTIC, SDIP-32
文件頁數(shù)： 68/120頁
文件大?。?/td> 1743K
代理商： TMP86CH09NG
Page 40
3. Interrupt Control Circuit
3.5 Software Interrupt (INTSW)
TMP86FH09ANG
3.4.3 Interrupt return
Interrupt return instructions [RETI]/[RETN] perform as follows.
As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to
restarting address, during interrupt service program.
Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and
INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and
PCH are located on address (SP + 1) and (SP + 2) respectively.
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter-
rupt can be accepted immediately after the interrupt return instruction is executed.
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter-
rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example
2).
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
task is performed but not the main task.
3.5 Software Interrupt (INTSW)
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
is highest prioritized interrupt).
Use the SWI instruction only for detection of the address error or for debugging.
3.5.1 Address error detection
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is gener-
ated and an address error is detected. The address error detection range can be further expanded by writing
FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM, DBR or SFR areas.
[RETI]/[RETN] Interrupt Return
1. Program counter (PC) and program status word
(PSW, includes IMF) are restored from the stack.
2. Stack pointer (SP) is incremented by 3.
Example 1 :Returning from address trap interrupt (INTATRAP) service program
PINTxx:
POP
WA
; Recover SP by 2
LD
WA, Return Address
;
PUSH
WA
; Alter stacked data
(interrupt processing)
RETN
; RETURN
Example 2 :Restarting without returning interrupt
(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)
PINTxx:
INC
SP
; Recover SP by 3
INC
SP
;
INC
SP
;
(interrupt processing)
LD
EIRL, data
; Set IMF to “1” or clear it to “0”
JP
Restart Address
; Jump into restarting address
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