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參數(shù)資料
| 型號： | TMDXCNCD28069ISO |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 89/174頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL PICCOLO CONTROLCARD |
| 標準包裝： | 1 |
| 系列： | TMS320F2806x, Piccolo™, C2000™ |
| 主要目的： | 接口，RS232，GPIO |
| 嵌入式： | 是，MCU，32 位 |
| 已用 IC / 零件： | TMS320F2806x |
| 已供物品： | 板 |
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SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
2.4
Signal Descriptions
Table 2-5 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at
reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate
functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs
are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled
or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins
are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do not
have an internal pullup.
NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38
pins could glitch during power up. If this is unacceptable in an application, 1.8 V could be supplied
externally. There is no power-sequencing requirement when using an external 1.8-V supply. However, if
the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.9-V
transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power
up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins, ensuring that
the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.
Table 2-5. Terminal Functions(1)
PIN NO.
PIN NAME
I/O/Z
DESCRIPTION
PZ
PN
PZP
PFP
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system
control of the operations of the device. If this signal is not connected or driven low, the
device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active-high test pin and must be maintained low at all times during
TRST
12
10
I
normal device operation. An external pull-down resistor is required on this pin. The
value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-k
resistor generally offers adequate protection. Since
this is application-specific, it is recommended that each target board be validated for
proper operation of the debugger and the application. (
↓)
TCK
See GPIO38
I
See GPIO38. JTAG test clock with internal pullup. (
↑)
See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control
TMS
See GPIO36
I
input is clocked into the TAP controller on the rising edge of TCK. (
↑)
See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the
TDI
See GPIO35
I
selected register (instruction or data) on a rising edge of TCK. (
↑)
See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected
TDO
See GPIO37
O/Z
register (instruction or data) are shifted out of TDO on the falling edge of TCK.
(8-mA drive)
FLASH
VDD3VFL
46
37
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
TEST2
45
36
I/O
Test Pin. Reserved for TI. Must be left unconnected.
(1)
I = Input, O = Output, Z = High Impedance, OD = Open Drain,
↑ = Pullup, ↓ = Pulldown
Copyright 2010–2012, Texas Instruments Incorporated
Device Overview
21
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