參數(shù)資料
型號: TMDXCNCD28069ISO
廠商: Texas Instruments
文件頁數(shù): 160/174頁
文件大小: 0K
描述: EVAL PICCOLO CONTROLCARD
標(biāo)準(zhǔn)包裝: 1
系列: TMS320F2806x, Piccolo™, C2000™
主要目的: 接口,RS232,GPIO
嵌入式: 是,MCU,32 位
已用 IC / 零件: TMS320F2806x
已供物品:
ADCSOCAO
ADCSOCBO
or
t
w(ADCSOCL)
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
5.10.1.2 ADC Start-of-Conversion Electrical Data/Timing
Table 5-20. External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(HCO )
cycles
Figure 5-16. ADCSOCAO or ADCSOCBO Timing
5.10.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
Table 5-21. ADC Electrical Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
Resolution
12
Bits
ADC clock
90-MHz device
0.001
45
MHz
Sample Window
7
64
ADC
Clocks
ACCURACY
INL (Integral nonlinearity)(1)
–4
4
LSB
DNL (Differential nonlinearity), no missing codes
–1
1.5
LSB
Offset error (2)
Executing a single self-
–20
20
LSB
recalibration(3)
Executing periodic self-
–4
4
recalibration(4)
Overall gain error with internal reference
–60
60
LSB
Overall gain error with external reference
–40
40
LSB
Channel-to-channel offset variation
–4
4
LSB
Channel-to-channel gain variation
–4
4
LSB
ADC temperature coefficient with internal reference
–50
ppm/°C
ADC temperature coefficient with external reference
–20
ppm/°C
VREFLO
–100
A
VREFHI
100
A
ANALOG INPUT
Analog input voltage with internal reference
0
3.3
V
Analog input voltage with external reference
VREFLO
VREFHI
V
VREFLO input voltage
(5)
VSSA
0.66
V
VREFHI input voltage
(6)
2.64
VDDA
V
with VREFLO = VSSA
1.98
VDDA
Input capacitance
5
pF
Input leakage current
±2
μA
(1)
INL will degrade when the ADC input voltage goes above VDDA.
(2)
1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3)
For more details, see the TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064,
TMS320F28063, TMS320F28062 Piccolo MCU Silicon Errata (literature number SPRZ342).
(4)
Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error.
(5)
VREFLO is always connected to VSSA on the 80-pin PN and PFP devices.
(6)
VREFHI must not exceed VDDA when using either internal or external reference modes. Since VREFHI is tied to ADCINA0 on the 80-pin PN
and PFP devices, the input signal on ADCINA0 must not exceed VDDA.
86
Peripheral and Electrical Specifications
Copyright 2010–2012, Texas Instruments Incorporated
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