參數(shù)資料
型號(hào)： TMDXCNCD28069ISO
廠商： Texas Instruments
文件頁數(shù)： 110/174頁
文件大小： 0K
描述： EVAL PICCOLO CONTROLCARD
標(biāo)準(zhǔn)包裝： 1
系列： TMS320F2806x, Piccolo™, C2000™
主要目的： 接口，RS232，GPIO
嵌入式： 是，MCU，32 位
已用 IC / 零件： TMS320F2806x
已供物品： 板
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
2.6
Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Peripheral Frame 3: McBSP registers are mapped to this. See Table 2-11.
Table 2-8. Peripheral Frame 0 Registers(1)
NAME
ADDRESS RANGE
SIZE (×16)
EALLOW PROTECTED(2)
Device Emulation Registers
0x00 0880 – 0x00 0984
261
Yes
System Power Control Registers
0x00 0985 – 0x00 0987
3
Yes
FLASH Registers(3)
0x00 0A80 – 0x00 0ADF
96
Yes
Code Security Module Registers
0x00 0AE0 – 0x00 0AEF
16
Yes
ADC registers
0x00 0B00 – 0x00 0B0F
16
No
(0 wait read only)
CPU–TIMER0, CPU–TIMER1, CPU–TIMER2
0x00 0C00 – 0x00 0C3F
64
No
Registers
PIE Registers
0x00 0CE0 – 0x00 0CFF
32
No
PIE Vector Table
0x00 0D00 – 0x00 0DFF
256
Yes
DMA Registers
0x00 1000 – 0x00 11FF
512
Yes
CLA Registers
0x00 1400 – 0x00 147F
128
Yes
CLA to CPU Message RAM (CPU writes ignored)
0x00 1480 – 0x00 14FF
128
NA
CPU to CLA Message RAM (CLA writes ignored)
0x00 1500 – 0x00 157F
128
NA
(1)
Registers in Frame 0 support 16-bit and 32-bit accesses.
(2)
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3)
The Flash Registers are also protected by the Code Security Module (CSM).
40
Device Overview
Copyright 2010–2012, Texas Instruments Incorporated
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