參數(shù)資料
型號(hào)： TMDXCNCD28069ISO
廠商： Texas Instruments
文件頁數(shù)： 152/174頁
文件大?。?/td> 0K
描述： EVAL PICCOLO CONTROLCARD
標(biāo)準(zhǔn)包裝： 1
系列： TMS320F2806x, Piccolo™, C2000™
主要目的： 接口，RS232，GPIO
嵌入式： 是，MCU，32 位
已用 IC / 零件： TMS320F2806x
已供物品： 板
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
5.9
Control Law Accelerator (CLA) Overview
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-
critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA
enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks
frees up the main CPU to perform other system and communication functions concurently. The following is
a list of major features of the CLA.
Clocked at the same rate as the main CPU (SYSCLKOUT).
An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
–
Complete bus architecture:
Program address bus and program data bus
Data address bus, data read bus, and data write bus
–
Independent eight-stage pipeline.
–
12-bit program counter (MPC)
–
Four 32-bit result registers (MR0–MR3)
–
Two 16-bit auxillary registers (MAR0, MAR1)
–
Status register (MSTF)
Instruction set includes:
–
IEEE single-precision (32-bit) floating-point math operations
–
Floating-point math with parallel load or store
–
Floating-point multiply with parallel add or subtract
–
1/X and 1/sqrt(X) estimations
–
Data type conversions.
–
Conditional branch and call
–
Data load and store operations
The CLA program code can consist of up to eight tasks or interrupt service routines.
–
The start address of each task is specified by the MVECT registers.
–
No limit on task size as long as the tasks fit within the CLA program memory space.
–
One task is serviced at a time through to completion. There is no nesting of tasks.
–
Upon task completion, a task-specific interrupt is flagged within the PIE.
–
When a task finishes, the next highest-priority pending task is automatically started.
Task trigger mechanisms:
–
C28x CPU via the IACK instruction
–
Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example:
Task1: ADCINT1 or EPWM1_INT
Task2: ADCINT2 or EPWM2_INT
Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT
Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT
–
Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT.
Memory and Shared Peripherals:
–
Two dedicated message RAMs for communication between the CLA and the main CPU.
–
The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
–
The CLA has direct access to the ADC Result registers, comparator registers, and the eCAP,
eQEP, and ePWM+HRPWM registers.
Copyright 2010–2012, Texas Instruments Incorporated
Peripheral and Electrical Specifications
79
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