參數(shù)資料
型號(hào)： TMDXCNCD28069ISO
廠商： Texas Instruments
文件頁數(shù)： 100/174頁
文件大?。?/td> 0K
描述： EVAL PICCOLO CONTROLCARD
標(biāo)準(zhǔn)包裝： 1
系列： TMS320F2806x, Piccolo™, C2000™
主要目的： 接口，RS232，GPIO
嵌入式： 是，MCU，32 位
已用 IC / 零件： TMS320F2806x
已供物品： 板
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
2.5.3
Viterbi, Complex Math, CRC Unit (VCU)
The C28x VCU enhances the processing power of C2000 devices by adding additional assembly
instructions to target complex math, Viterbi decode, and CRC calculations. The VCU instructions
accelerate many applications, including the following:
Orthogonal frequency-division multiplex (OFDM) used in the PRIME and G3 standards for power line
communications
Short-range radar complex math calculations
Power calculations
Memory and data communication packet checks (CRC)
The VCU features include:
Instructions to support Cyclic Redundancy Checks (CRCs), which is a polynomial code checksum.
–
CRC8
–
CRC16
–
CRC32
Instructions to support a flexible software implementation of a Viterbi decoder
–
Branch metric calculations for a code rate of 1/2 or 1/3
–
Add-Compare Select or Viterbi Butterfly in 5 cycles per butterfly
–
Traceback in 3 cycles per stage
–
Easily supports a constraint length of K = 7 used in PRIME and G3 standards
Complex math arithmetic unit
–
Single-cycle Add or Subtract
–
2-cycle multiply
–
2-cycle multiply and accumulate (MAC)
–
Single-cycle repeat MAC
Independent register space
2.5.4
Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and
data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus
accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the
memory bus.)
Program Writes
(Simultaneous data and program writes cannot occur on the
memory bus.)
Data Reads
Program Reads
(Simultaneous program reads and fetches cannot occur on the
memory bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur on the
memory bus.)
Copyright 2010–2012, Texas Instruments Incorporated
Device Overview
31
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