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參數(shù)資料
| 型號： | TLC320AD80C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Audio Processor Subsystem |
| 中文描述： | 音頻處理器子系統(tǒng) |
| 文件頁數(shù)： | 27/36頁 |
| 文件大小： | 219K |
| 代理商： | TLC320AD80C |
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3–5
3.4
Timing Requirements, T
A
= 25
°
C, AV
DD
= DV
DD
= 5 V
±
5%, f
s
= 48 kHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input frequency,
MCLK1, MCLK2
4.096
18.432
MHz
fs
tsu1
th1
tsu2
th2
Audio sample rate
8
48
kHz
Setup time, PCM data
Relative to the rising edge of BCLK
60
ns
Hold time, PCM data
Relative to the rising edge of BCLK
0
ns
Setup time, LRCLK
Relative to the rising edge of BCLK
60
ns
Hold time, LRCLK
Relative to the rising edge of BCLK
0
ns
3.4.1
Serial PCM Data Port (see Figures 3–1 and 3–2)
PARAMETER
MIN
TYP
MAX
UNITS
tc(BCLK)
tr(BCLK)
tf(BCLK)
tsu(LRCLK)
th(LRCLK)
tsu(SDATA)
th(SDATA)
td(SDATA)
twL(BCLK)
twH(BCLK)
twL(MCLK)
twH(MCLK)
tr(MCLK)
tf(MCLK)
Cycle time, BCLK
60
ns
Rise time, BCLK
0
ns
Fall time, BCLK
Setup time, LRCLK
↓
before BCLK
↑
Hold time, LRCLK
↑
after BCLK
↑
Setup time, SDATA before BCLK
↑
Hold time, SDATA after BCLK
↑
Delay time, SDATA valid after BCLK
↓
Pulse duration, BCLK low
0
ns
0
ns
0
ns
0
ns
0
ns
0
ns
60
ns
Pulse duration, BCLK high
60
ns
Pulse duration, MCLK low
60
ns
Pulse duration, MCLK high
60
ns
Rise time, MCLK
0
ns
Fall time, MCLK
0
ns
3.4.2
Serial Control Interface, T
A
= 25
°
C, AV
DD
= DV
DD
= 5 V
±
5%, (see Figure 3–3)
DESCRIPTION
MIN
TYP
MAX
UNITS
fSCLK
tc(SCLK)
twL(SCLK)
twH(SCLK)
tsu(CS)
th(CS)
tsu(CDIN)
th(CDIN)
td(CDOUT)
th(CDOUT)
tr(SCLK)
tf(SCLK)
Input frequency, SCLK
3
MHz
Cycle time, SCLK
333
ns
Pulse width, SCLK low
100
ns
Pulse width, SCLK high
Setup time, CS
↓
before SCLK
↓
Hold time, CS
↑
after SCLK
↑
Setup time, CDIN before SCLK
↑
Hold time, CDIN after SCLK
↑
Delay time, CDOUT after SCLK
↓
Hold time, CDOUT after SCLK
↓
Rise time, SCLK
100
ns
150
ns
150
ns
50
ns
50
ns
30
ns
5
ns
100
ns
Fall time, SCLK
100
ns
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