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參數(shù)資料
| 型號： | TLC320AD80C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Audio Processor Subsystem |
| 中文描述： | 音頻處理器子系統(tǒng) |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 219K |
| 代理商： | TLC320AD80C |
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2–3
2.1.1.1
The main serial PCM (SDATA, BCLK, and LRCLK) port always operates in slave mode. That is, all clocks
are inputs to the device. The LRCLK and BCLK clocks must be synchronous with MCLK.
Main Serial PCM Port
A typical set-top-box application would connect this input to an MPEG/AC3 audio decoder.
2.1.1.2
The aux serial port (ASDATA, ABCLK, and ALRCLK) operates in either the master or slave mode. The
master mode supports all the documented interface protocols with the exception of the DSP mode. The
slave mode supports all documented protocols without exception.
Aux Serial PCM Data Port
The aux serial PCM data port receives non-compressed data from an auxillary audio source. The slave
mode is identical to the clock mode of main serial PCM port. In the master mode, this device generates the
required BCLK and LRCLK clocks synchronously with the applied MCLK.
2.1.1.3
The serial ports comprise the signals in Table 2–1.
Serial Interface Protocols Supported
Table 2–1. Serial Port Signals
MAIN PORT
AUXILIARY PORT
DESCRIPTION
SDATA
ASDATA
PCM audio data. 16-bit or 18-bit data precision
BCLK
ABCLK
Bit clock. Rate is equal to 32x, 48x, or 64x the sample rate
LRCLK
ALRCLK
Left/right clock. Rate is equal to the sample rate
Figure 2–1 through Figure 2–4 are for a bit clock (BCLK) set to 48
precision. All serial protocols supported are shown.
the sample rate and 16-bit data
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
16
17
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
16
17
Left Channel
Right Channel
LRCLK
BCLK
SDATA
16 Bit
SDATA
18 Bit
X X X
X X X X X X X X
X X X X X X X
X
X X X
X X X X X X
X X X X X
X
Figure 2–1. Philips I
2
S Protocol Serial PCM Data Format
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
16
17
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
15 14 13 12 11 10 9
8 7
6
5
4
3
2 1 0
16
17
Left Channel
Right Channel
LRCLK
BCLK
SDATA
16 Bit
SDATA
18 Bit
X X
X X X X X X X X
X X X X X X X X X
X X
X X X X X X
X X X X X X X
Figure 2–2. Left-Justified Serial PCM Data Format
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD80CPM | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC320AD81C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio Digital Equalizer DC |
| TLC320AD81CDBT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| TLC320AD90 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio Codec |
| TLC320AD91 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio Codec |
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