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參數(shù)資料
| 型號： | TLC2943DB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK |
| 中文描述： | 高效能雙鎖相環(huán)積木 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大小： | 425K |
| 代理商： | TLC2943DB |
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, V
DD
= 3 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VOH
VOL
V(TH+)
II
Z(VCOIN)
IDD(INH)
IDD(VCO)
NOTES:
High-level output voltage
IOH = –2 mA
IOL = 2 mA
2.4
V
Low-level output voltage
0.3
V
Positive input threshold voltage
0.9
1.5
2.1
±
1
V
μ
A
M
μ
A
mA
Input current
VI = VDD or GND
VCOIN = 1/2VDD
See Note 5
VCOIN input impedance
10
VCO supply current (inhibit) (for one chip)
0.01
1
VCO supply current (for one chip)
See Note 6
5.1
15
5. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.
6. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD , RBIAS = 2.4 k
, VCO INHIBIT = ground, and PFD INHIBIT
is high.
PFD section
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VOH
VOL
IOZ
VIH
VIL
High-level output voltage
IOH = –2 mA
IOL = 2 mA
PFD INHIBIT = high,
2.7
V
Low-level output voltage
0.2
±
1
V
μ
A
V
High-impedance state output current
VO = VDD or GND
High-level input voltage at FIN–A, FIN–B
Low-level input voltage at FIN–A, FIN–B
Positive input threshold voltage at PFD
INHIBIT
2.1
0.9
V
V(TH+)
0.9
1.5
2.1
V
CI
ZI
IDD(PFD)
NOTE 7: The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (V I(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT open,
and VCO OUT is inhibited.
Input capacitance at FIN–A, FIN–B
Input impedance at FIN–A, FIN–B
PFD supply current
5
pF
M
mA
10
See Note 7
0.7
4
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