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| 型號： | TLC2943DB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK |
| 中文描述： | 高效能雙鎖相環(huán)積木 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大小： | 425K |
| 代理商： | TLC2943DB |
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
gain of VCO and PFD
Figure 18 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The K
p
and K
V
values are obtained from the operating
characteristics of the device as shown in
Figure 18. K
p
is defined from the phase detector
V
OL
and V
OH
specifications and the equation
shown in Figure 18(b). K
V
is defined from
Figures 8, 9, 10, and 11 as shown in Figure 18(c).
The parameters for the block diagram with the
units are as follows:
K
V
: VCO gain (rad/s/V)
K
p
: PFD gain (V/rad)
K
f
: LPF gain (V/V)
K
N
: countdown divider gain (1/N)
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
R
BIAS
The external bias resistor sets the VCO center frequency with 1/2 V
DD
applied to the VCO IN terminal. For the
most accurate results, a metal-film resistor is the better choice, but a carbon-composition resistor can also be
used with excellent results. A 0.22
μ
F capacitor should be connected from the BIAS terminal to ground as close
to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 17 is as follows:
H
0.8 Kp
KV
Kf(
)
Where
K
f
(
∞
) = the filter transfer function value at
ω
=
∞
(1)
Divider
(KN = 1/N)
PFD
(Kp)
VCO
(KV)
LPF
(Kf)
TLC2933
f REF
VOH
fMAX
fMIN
VIN MIN
VIN MAX
–2
π
2
π
–
π
0
π
Range of
Comparison
VOH
VOL
Kp =
VOH – VOL
4
π
KV =
2
π
(fMAX – fMIN)
VIN MAX – VIN MIN
(c)
Figure 18. Example of a PLL Block Diagram
(a)
(b)
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