參數資料
型號： TLC2943DB
廠商： Texas Instruments, Inc.
英文描述： HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
中文描述： 高效能雙鎖相環(huán)積木
文件頁數： 5/27頁
文件大小： 425K
代理商： TLC2943DB
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
phase frequency detector (PFD)
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to F
IN
-A and F
IN
-B as shown in Figure 2. Nominally the
reference is supplied to F
IN
-A, and the frequency from the external counter output is fed to F
IN
-B. For clock
recovery PLL systems, other types of phase detectors should be used.
FIN-A_1, 2
FIN-B_1, 2
PFD_1, 2 OUT
VOH
HI-Z
VOL
Figure 2. PFD Function Timing Chart
PFD output control
A high level on PFD INHIBIT places the PFD OUT in the high impedance state and the PFD stops phase
detection as shown in Table 3 and Table 4. A high level on PFD inhibit also can be used as the power-down mode
for the PFD.
Table 3. PFD_1 Inhibit Function
PFD_1 INHIBIT
PFD_1
PFD_1 OUT
PFD_1 IDD
Normal
Low
Active
Active
High
Stop
Hi-Z
Power down
Table 4. PFD_2 Inhibit Function
PFD_2 INHIBIT
PFD_2
PFD_2 OUT
PFD_2 IDD
Normal
Low
Active
Active
High
Stop
Hi-Z
Power down
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