參數(shù)資料
型號： TLC2943DB
廠商： Texas Instruments, Inc.
英文描述： HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
中文描述： 高效能雙鎖相環(huán)積木
文件頁數(shù)： 3/27頁
文件大?。?/td> 425K
代理商： TLC2943DB
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
8, 31
GND
Common GND for chip 1
12, 27
Common GND for chip 2
FIN–A_1,
FIN–B_1
4
5
I
Reference frequency signal input and comparison frequency signal input for PFD_1. fREF–IN_1 inputs
to FIN-A_1, and comparison frequency input from external counter logic to FIN–B_1, for a lag-lead filter
use as LPF.
FIN–A_2,
FIN–B_2
16
17
I
Reference frequency signal input and comparison frequency signal input for PFD_2. fREF–IN_2 inputs
to FIN-A_2, and comparison frequency input from external counter logic to FIN-B_2, for a lag-lead filter use
as LPF.
LOGIC_1 GND
7
Ground for the internal logic of chip 1
LOGIC_2 GND
19
Ground for the internal logic of chip 2
LOGIC_1 VDD
1
Power supply for the internal logic of chip 1. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.
LOGIC_2 VDD
13
Power supply for the internal logic of chip 2. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.
NC
9, 10,
11, 20,
28, 29,
30, 32
No internal connection
PFD_1 INHIBIT
33
I
PFD inhibit control for chip 1. When PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state,
see Table 2.
PFD_2 INHIBIT
21
I
PFD inhibit control for chip 2. When PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state,
see Table 2.
PFD_1 OUT
6
O
PFD output of chip 1. When the PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state.
PFD_2 OUT
18
O
PFD output of chip 2. When the PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state.
RBIAS_1
37
I
Bias supply for VCO_1. An external resistor (RBIAS) between VCO_1 VDD and BIAS_1 supplies bias for
adjusting the oscillation frequency range of VCO_1.
RBIAS_2
25
I
Bias supply for VCO_2. An external resistor (RBIAS) between VCO_2 VDD and BIAS_2 supplies bias for
adjusting the oscillation frequency range of VCO_2.
TEST_1
2
Test terminal. TEST connects to LOGIC_1 GND for normal operation.
TEST_2
14
Test terminal. TEST connects to LOGIC_2 GND for normal operation.
VCO_1 GND
35
GND for VCO_1
VCO_2 GND
23
GND for VCO_2
VCO_1 INHIBIT
34
I
VCO inhibit control for chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low (see Table 1).
VCO_2 INHIBIT
22
I
VCO inhibit control for chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low (see Table 1).
VCO_1 OUT
3
O
VCO output of chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low.
VCO_2 OUT
15
O
VCO output of chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low.
VCO_1 VDD
38
Power supply for VCO_1. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.
VCO_2 VDD
26
Power supply for VCO_2. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.
VCOIN_1
36
I
VCO_1 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
VCOIN_2
24
I
VCO_2 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
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