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參數(shù)資料
| 型號(hào)： | TLC2943DB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK |
| 中文描述： | 高效能雙鎖相環(huán)積木 |
| 文件頁數(shù)： | 25/27頁 |
| 文件大?。?/td> | 425K |
| 代理商： | TLC2943DB |
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
PCB layout considerations
The TLC2943 contains high frequency analog oscillators; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2943 user:
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
LOGIC V
DD
and VCO V
DD
should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
VCO V
DD
to GND and LOGIC V
DD
to GND should be decoupled with a 0.1-
μ
F capacitor placed as close
as possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to GND.
The evaluation and operation schematic for the TLC2943 is shown in Figure 22.
Phase
Comparator
AGND
DGND
DGND
DGND
REF IN
DVDD
AVDD
VDD
LOGIC VDD (digital)
LOGIC GND (Digital)
TEST
FIN–A
VCOINHIBIT
PFD INHIBIT
GND
VCO GND
VCOIN
BIAS
VCO VDD
VCO
R1
R3
C1
R2
C2
R5
R6
S1
S2
Divide
By
N
0.22
μ
F
1
2
3
4
5
6
7
38
37
36
35
34
33
31
FIN–B
RBIAS resistor
VCO OUT
PFD OUT
PLL2
PLL1
Figure 22. Evaluation and Operation Schematic
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