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參數(shù)資料
| 型號： | TL16PNP100APT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, QFP-48 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 304K |
| 代理商： | TL16PNP100APT |
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
PnP logical device control registers
The registers in Table 4 are repeated for each logical device. These registers control device functions, such as
enabling the device onto the ISA bus.
Table 4. PnP Logical Device Control Registers
ADDRESS PORT
VALUE
REGISTER NAME VALUE
READ/WRITE
CAPABILITY
POWER UP
0
×30
ACTIVE
Read/write
00 00 00 00
This register controls whether the logical device is active on the bus.
Bits 7–1
These bits are reserved and must be set to zero.
Bit 0
If set, bit 0 activates the logical device.
An inactive device does not respond to nor drive any ISA bus signals. Before a logical device is activated, I/O range check
must be disabled.
0
×31
I/O RANGE CHECK
Read/write
00 00 00 00
This register is used to perform a conflict check on the I/O port range programmed for use by the logical device.
Bits 7–2
These bits are reserved and must be set to zero.
Bit 1
If set to 1, bit 1 I/O range check is enabled. I/O range check is only valid when the logical device is
inactive.
Bit 0
If set to 1, the logical device responds to I/O read operations to its assigned I/O range with a 0
×55 when
I/O range check is in operation. If clear, the logical device responds with a 0
×AA.
PnP logical device configuration registers
The registers in Table 5 are repeated for each logical device and are used to program the ISA bus resource use
of the device.
Table 5. PnP Logical Device Configuration Registers
ADDRESS PORT
VALUE
REGISTER NAME VALUE
READ/WRITE
CAPABILITY
POWER UP
0
×60
I/O PORT BASE ADDRESS [15–8]
Read/write
00
This register indicates the selected I/O lower limit address bits [15–8] for I/O descriptor 0. When the device is activated,
if there is an address match to register 0
×61 and an address match to this register, a chip select is generated to the logical
device.
Bits 7–2
Bits 15 – 10 are not supported, since the logical device uses 10-bit address decoding.
Bits 1–0
Bits 1–0 have address bits 9 and 8 are indicated here.
0
×61
I/O PORT BASE ADDRESS [7–0]
Read/write
00 00 00 00
This register indicates the selected I/O lower limit address bits [7–0] for I/O descriptor 0. When the device is activated, if
there is an address match to register 0
×60 and an address match to this register, a chip select is generated to the logical
device.
Bits 7–0
Address bits 7– 0 are indicated here.
0
×70
INTERRUPT REQUEST LEVEL SELECT
Read/write
00 00
This register indicates the selected interrupt level.
Bits 3–0
These bits select the interrupt level. This device uses 6 interrupts from IRQ3 to IRQ7 and IRQ9.
0
×71
INTERRUPT REQUEST TYPE
Read/write
00 00
This register indicates which type of interrupt is used for the selected interrupt level.
Bit 7–2
These bits are reserved.
Bit 1
This bit is level, where 1 = high, 0 = low
Bit 0
This bit is type, where 1 = level, 0 = edge
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