參數(shù)資料
型號(hào): TL16PNP100APT
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP48
封裝: PLASTIC, QFP-48
文件頁數(shù): 18/21頁
文件大?。?/td> 304K
代理商: TL16PNP100APT
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
td1
Delay time, CS high to SCLK high
tSHCH
See Figure 8
50
ns
td2
Delay time, SIO input valid to SCLK high
tDVCH
See Figure 8 and Fig
100
ns
tpd1
Propagation delay time, SCLK high to SIO level transi-
tion
tCHDX
See Figure 8 and Fig-
ure 9
100
ns
tpd2
Propagation delay time, SCLK high to output valid
tCHQV
500
ns
tpd3
Propagation delay time, SCLK low to CS transition
tCLSL
See Figure 9
2
clock
period
td3
Delay time, CS low to D/Q output Hi-Z
tSLQZ
100
ns
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
tw1
Pulse duration, write strobe, IOW low
tWR
See Figure 5
2
clock
periods
tw2
Pulse duration, read strobe, IOR low
tRD
See Figure 6
3
clock
periods
tw3
Pulse duration, master reset
tMR
1
s
tsu1
Setup time, data D7–D0 valid before
IOW↑
tDS
See Figure 5
15
ns
th1
Hold time, chip select CSx valid after address
A0–A11 becomes invalid
tCH
From the first rising edge of XIN
after address becomes invalid,
See Figure 5 and Figure 6
20
ns
th2
Hold time, data valid D7–D0 after IOW
tDH
See Figure 5
5
ns
td4
Delay time, CSx valid after address A0–A11 valid
tCSRW
From the first rising edge of XIN
after address valid,
See Figure 5 and Figure 6
30
ns
th3
Hold time, address A0–A11 valid after
IOW↑
tAW
See Figure 5
5
ns
td5
Delay time, IOR valid to data D0–D7 valid
tCSVD
CL = 45 pF after 2 clock periods,
See Figure 6
30
ns
td6
Delay time,
IOR↑ to floating data D0–D7
tHZ
CL = 45 pF,
See Figure 6
20
ns
td7
Delay time, INTR0
↑, INTR1↑, INTR0↓, or INTR1↓
to IRQ
↑ or IRQ↓
See Figure 7
15
ns
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