參數(shù)資料
型號(hào)： TL16PNP100APT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP48
封裝： PLASTIC, QFP-48
文件頁(yè)數(shù)： 17/21頁(yè)
文件大?。?/td> 304K
代理商： TL16PNP100APT
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.75
5
5.25
V
High-level input voltage, VIH
2
VCC
V
Low-level input voltage, VIL
– 0.5
0.8
V
Operating free-air temperature, TA
0
70
°C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High level output voltage
IOH = – 4 mA (see Note 1)
VCC – 0.8
V
VOH
High-level output voltage
IOH = – 12 mA (see Note 2)
VCC – 0.8
V
VOL
Low level output voltage
IOL = 4 mA (see Note 1)
0.5
V
VOL
Low-level output voltage
IOL = 24 mA (see Note 2)
0.5
V
Il
Input current
VCC = 5.25 V,
VSS = 0,
All other terminals
±1
A
Il
Input current
CC
,
VI = 0 to 5.25 V,
All other terminals
floating
±1
A
High impedance state output cur
VCC = 5.25 V,
VSS = 0,
IOZ
High-impedance-state output cur-
rent
VCC 5.25 V,
VSS 0,
VO = 0 to 5.25 V,
±10
A
OZ
rent
O
Pullup transistors and pulldown transistors are off
VCC =5 25 V
TA =25°C
VCC = 5.25 V,
TA = 25°C,
ICC
Supply current
All inputs at 0.8 V,
CLK at 4 MHz,
0.7
mA
ICC
Su
ly current
All in uts at 0.8 V,
CLK at 4 MHz,
No load on outputs
0.7
mA
No load on outputs
Ci(CLK)
Clock input capacitance
15
20
pF
fCLK
Clock frequency
10
22
MHz
All typical values are at VCC = 5 V and TA = 25°C.
NOTES:
1. These parameters apply for all outputs except D7 – D0, IRQ3 – IRQ7 and IRQ9.
2. These parameters only apply for D7 – D0 and IRQ3 – IRQ7 and IRQ9 outputs.
clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
tw(SCLKH)
Pulse duration, SCLK high to low (see Note 3)
tCHCL
250
ns
tw(SCLKL)
Pulse duration, SCLK low to high (see Note 3)
tCLCH
See Figure 8
250
ns
fCLK
SCLK clock frequency (see Note 4)
0.3
0.68
MHz
NOTES:
3. The ST93C56 chip select, S, must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles according
to the ST93C56 specification.
4. The SCLK signal is attained by internally dividing the frequency of the XIN signal by 32.
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